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asmicon: skeleton

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commit 7b14e0bd057d0c561e0b14dc1d7343707a9c8e43 1 parent 8d4a428
Sébastien Bourdeauducq authored
62  milkymist/asmicon/__init__.py
... ...
@@ -0,0 +1,62 @@
  1
+from migen.fhdl.structure import *
  2
+from migen.bus import dfi, asmibus
  3
+
  4
+from milkymist.asmicon.refresher import *
  5
+from milkymist.asmicon.bankmachine import *
  6
+from milkymist.asmicon.multiplexer import *
  7
+
  8
+class PhySettings:
  9
+	def __init__(self, dfi_a, dfi_ba, dfi_d, nphases, rdphase, wrphase):
  10
+		self.dfi_a = dfi_a
  11
+		self.dfi_ba = dfi_ba
  12
+		self.dfi_d = dfi_d
  13
+		self.nphases = nphases
  14
+		self.rdphase = rdphase
  15
+		self.wrphase = wrphase
  16
+
  17
+class GeomSettings:
  18
+	def __init__(self, row_a, col_a):
  19
+		self.row_a = row_a
  20
+		self.col_a = col_a
  21
+
  22
+class TimingSettings:
  23
+	def __init__(self, tREFI, tRFC):
  24
+		self.tREFI = tREFI
  25
+		self.tRFC = tRFC
  26
+
  27
+class ASMIcon:
  28
+	def __init__(self, phy_settings, geom_settings, timing_settings, time=0):
  29
+		self.phy_settings = phy_settings
  30
+		self.geom_settings = geom_settings
  31
+		self.timing_settings = timing_settings
  32
+		self.finalized = False
  33
+		
  34
+		self.dfi = dfi.Interface(self.phy_settings.dfi_a,
  35
+			self.phy_settings.dfi_ba,
  36
+			self.phy_settings.dfi_d,
  37
+			self.phy_settings.nphases)
  38
+		burst_length = self.phy_settings.nphases*2
  39
+		self.address_align = log2_int(burst_length)
  40
+		aw = self.phy_settings.dfi_ba + self.geom_settings.row_a + self.geom_settings.col_a - self.address_align
  41
+		dw = self.phy_settings.dfi_d*self.phy_settings.nphases
  42
+		self.hub = asmibus.Hub(aw, dw, time)
  43
+	
  44
+	def finalize(self):
  45
+		if self.finalized:
  46
+			raise FinalizeError
  47
+		self.finalized = True
  48
+		self.hub.finalize()
  49
+		slots = self.hub.get_slots()
  50
+		self.refresher = Refresher(self.timing_settings)
  51
+		self.bank_machines = [BankMachine(self.geom_settings, self.timing_settings, self.address_align, i, slots) for i in range(2**self.phy_settings.dfi_ba)]
  52
+		self.multiplexer = Multiplexer(self.phy_settings, self.geom_settings, self.timing_settings,
  53
+			self.bank_machines, self.refresher,
  54
+			self.dfi, self.hub)
  55
+	
  56
+	def get_fragment(self):
  57
+		if not self.finalized:
  58
+			raise FinalizeError
  59
+		return self.hub.get_fragment() + \
  60
+			self.refresher.get_fragment() + \
  61
+			sum([bm.get_fragment() for bm in self.bank_machines], Fragment()) + \
  62
+			self.multiplexer.get_fragment()
8  milkymist/asmicon/bankmachine.py
... ...
@@ -0,0 +1,8 @@
  1
+from migen.fhdl.structure import *
  2
+
  3
+class BankMachine:
  4
+	def __init__(self, geom_settings, timing_settings, address_align, bankn, slots):
  5
+		pass
  6
+
  7
+	def get_fragment(self):
  8
+		return Fragment()
8  milkymist/asmicon/multiplexer.py
... ...
@@ -0,0 +1,8 @@
  1
+from migen.fhdl.structure import *
  2
+
  3
+class Multiplexer:
  4
+	def __init__(self, phy_settings, geom_settings, timing_settings, bank_machines, refresher, dfi, hub):
  5
+		pass
  6
+	
  7
+	def get_fragment(self):
  8
+		return Fragment()
8  milkymist/asmicon/refresher.py
... ...
@@ -0,0 +1,8 @@
  1
+from migen.fhdl.structure import *
  2
+
  3
+class Refresher:
  4
+	def __init__(self, timing_settings):
  5
+		pass
  6
+	
  7
+	def get_fragment(self):
  8
+		return Fragment()
41  top.py
... ...
@@ -1,10 +1,11 @@
1 1
 from fractions import Fraction
  2
+from math import ceil
2 3
 
3 4
 from migen.fhdl.structure import *
4 5
 from migen.fhdl import verilog, autofragment
5  
-from migen.bus import wishbone, asmibus, wishbone2asmi, csr, wishbone2csr, dfi
  6
+from migen.bus import wishbone, wishbone2asmi, csr, wishbone2csr, dfi
6 7
 
7  
-from milkymist import m1crg, lm32, norflash, uart, sram, s6ddrphy, dfii
  8
+from milkymist import m1crg, lm32, norflash, uart, sram, s6ddrphy, dfii, asmicon
8 9
 import constraints
9 10
 
10 11
 MHz = 1000000
@@ -12,9 +13,28 @@
12 13
 sram_size = 4096 # in bytes
13 14
 l2_size = 8192 # in bytes
14 15
 
15  
-dfi_a = 13
16  
-dfi_ba = 2
17  
-dfi_d = 64
  16
+clk_period_ns = 1000000000/clk_freq
  17
+def ns(t, margin=False):
  18
+	if margin:
  19
+		t += clk_period_ns/2
  20
+	return ceil(t/clk_period_ns)
  21
+
  22
+sdram_phy = asmicon.PhySettings(
  23
+	dfi_a=13,
  24
+	dfi_ba=2,
  25
+	dfi_d=64, 
  26
+	nphases=2,
  27
+	rdphase=0,
  28
+	wrphase=1
  29
+)
  30
+sdram_geom = asmicon.GeomSettings(
  31
+	row_a=13,
  32
+	col_a=10
  33
+)
  34
+sdram_timing = asmicon.TimingSettings(
  35
+	tREFI=ns(7800),
  36
+	tRFC=ns(70)
  37
+)
18 38
 
19 39
 def ddrphy_clocking(crg, phy):
20 40
 	names = [
@@ -31,16 +51,17 @@ def get():
31 51
 	#
32 52
 	# ASMI
33 53
 	#
34  
-	asmihub0 = asmibus.Hub(23, 128, 12) # TODO: get hub from memory controller
35  
-	asmiport_wb = asmihub0.get_port()
36  
-	asmihub0.finalize()
  54
+	asmicon0 = asmicon.ASMIcon(sdram_phy, sdram_geom, sdram_timing, 8)
  55
+	asmiport_wb = asmicon0.hub.get_port()
  56
+	asmicon0.finalize()
37 57
 	
38 58
 	#
39 59
 	# DFI
40 60
 	#
41  
-	ddrphy0 = s6ddrphy.S6DDRPHY(dfi_a, dfi_ba, dfi_d)
42  
-	dfii0 = dfii.DFIInjector(1, dfi_a, dfi_ba, dfi_d, 2)
  61
+	ddrphy0 = s6ddrphy.S6DDRPHY(sdram_phy.dfi_a, sdram_phy.dfi_ba, sdram_phy.dfi_d)
  62
+	dfii0 = dfii.DFIInjector(1, sdram_phy.dfi_a, sdram_phy.dfi_ba, sdram_phy.dfi_d, sdram_phy.nphases)
43 63
 	dficon0 = dfi.Interconnect(dfii0.master, ddrphy0.dfi)
  64
+	dficon1 = dfi.Interconnect(asmicon0.dfi, dfii0.slave)
44 65
 
45 66
 	#
46 67
 	# WISHBONE
1  verilog/s6ddrphy/s6ddrphy.v
... ...
@@ -1,7 +1,6 @@
1 1
 /*
2 2
  * 1:2 frequency-ratio DDR PHY for Spartan-6
3 3
  *
4  
- ************* DATAPATH SIGNALS ***********
5 4
  * Assert dfi_wrdata_en and present the data 
6 5
  * on dfi_wrdata_mask/dfi_wrdata in the same
7 6
  * cycle as the write command.

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