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framebuffer: use DMA controller from Migen

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commit 8222ee7f46ef53775dd319b9e82352c1281158cf 1 parent 43ac5c8
Sébastien Bourdeauducq authored April 30, 2013

Showing 1 changed file with 19 additions and 26 deletions. Show diff stats Hide diff stats

  1. 45  milkymist/framebuffer/__init__.py
45  milkymist/framebuffer/__init__.py
@@ -6,8 +6,8 @@
6 6
 from migen.flow.actor import *
7 7
 from migen.flow.network import *
8 8
 from migen.flow.transactions import *
9  
-from migen.flow import plumbing
10  
-from migen.actorlib import misc, dma_asmi, structuring, sim, spi
  9
+from migen.bank.description import CSRStorage
  10
+from migen.actorlib import dma_asmi, structuring, sim, spi
11 11
 
12 12
 _hbits = 11
13 13
 _vbits = 12
@@ -39,7 +39,7 @@
39 39
 ]
40 40
 
41 41
 class _FrameInitiator(spi.SingleGenerator):
42  
-	def __init__(self, asmi_bits, length_bits, alignment_bits):
  42
+	def __init__(self):
43 43
 		layout = [
44 44
 			("hres", _hbits, 640, 1),
45 45
 			("hsync_start", _hbits, 656, 1),
@@ -49,12 +49,9 @@ def __init__(self, asmi_bits, length_bits, alignment_bits):
49 49
 			("vres", _vbits, 480),
50 50
 			("vsync_start", _vbits, 492),
51 51
 			("vsync_end", _vbits, 494),
52  
-			("vscan", _vbits, 525),
53  
-			
54  
-			("base", asmi_bits, 0, alignment_bits),
55  
-			("length", length_bits, 640*480*4, alignment_bits)
  52
+			("vscan", _vbits, 525)
56 53
 		]
57  
-		spi.SingleGenerator.__init__(self, layout, spi.MODE_CONTINUOUS)
  54
+		spi.SingleGenerator.__init__(self, layout, spi.MODE_EXTERNAL)
58 55
 
59 56
 class VTG(Module):
60 57
 	def __init__(self):
@@ -171,17 +168,11 @@ def sim_fifo_gen():
171 168
 
172 169
 class Framebuffer(Module):
173 170
 	def __init__(self, pads, asmiport, simulation=False):
174  
-		asmi_bits = asmiport.hub.aw
175  
-		alignment_bits = bits_for(asmiport.hub.dw//8) - 1
176  
-		length_bits = _hbits + _vbits + 2 - alignment_bits
177 171
 		pack_factor = asmiport.hub.dw//(2*_bpp)
178 172
 		packed_pixels = structuring.pack_layout(_pixel_layout, pack_factor)
179 173
 		
180  
-		self._fi = fi = _FrameInitiator(asmi_bits, length_bits, alignment_bits)
181  
-		adrloop = misc.IntSequence(length_bits, asmi_bits)
182  
-		adrbuffer = AbstractActor(plumbing.Buffer)
183  
-		dma = dma_asmi.Reader(asmiport)
184  
-		datbuffer = AbstractActor(plumbing.Buffer)
  174
+		fi = _FrameInitiator()
  175
+		dma = spi.DMAReadController(dma_asmi.Reader(asmiport), spi.MODE_EXTERNAL, length_reset=640*480*4)
185 176
 		cast = structuring.Cast(asmiport.hub.dw, packed_pixels, reverse_to=True)
186 177
 		unpack = structuring.Unpack(pack_factor, _pixel_layout)
187 178
 		vtg = VTG()
@@ -191,18 +182,20 @@ def __init__(self, pads, asmiport, simulation=False):
191 182
 			fifo = FIFO()
192 183
 		
193 184
 		g = DataFlowGraph()
194  
-		g.add_connection(fi, adrloop, source_subr=["length", "base"])
195  
-		g.add_connection(adrloop, adrbuffer)
196  
-		g.add_connection(adrbuffer, dma)
197  
-		g.add_connection(dma, datbuffer)
198  
-		g.add_connection(datbuffer, cast)
  185
+		g.add_connection(fi, vtg, sink_ep="timing")
  186
+		g.add_connection(dma, cast)
199 187
 		g.add_connection(cast, unpack)
200 188
 		g.add_connection(unpack, vtg, sink_ep="pixels")
201  
-		g.add_connection(fi, vtg, sink_ep="timing", source_subr=[
202  
-			"hres", "hsync_start", "hsync_end", "hscan", 
203  
-			"vres", "vsync_start", "vsync_end", "vscan"])
204 189
 		g.add_connection(vtg, fifo)
205  
-		self.submodules._comp_actor = CompositeActor(g)
  190
+		self.submodules += CompositeActor(g)
  191
+
  192
+		self._enable = CSRStorage()
  193
+		self.comb += [
  194
+			fi.trigger.eq(self._enable.storage),
  195
+			dma.generator.trigger.eq(self._enable.storage),
  196
+		]
  197
+		self._fi = fi
  198
+		self._dma = dma
206 199
 		
207 200
 		# Drive pads
208 201
 		if not simulation:
@@ -216,4 +209,4 @@ def __init__(self, pads, asmiport, simulation=False):
216 209
 		self.comb += pads.psave_n.eq(1)
217 210
 
218 211
 	def get_csrs(self):
219  
-		return self._fi.get_csrs()
  212
+		return [self._enable] + self._fi.get_csrs() + self._dma.get_csrs()

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