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Remove explicit bus names

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commit 8a2646a54950248cfe28376ae06cb47f9053e77a 1 parent 28f00c3
@sbourdeauducq sbourdeauducq authored
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4 milkymist/lm32/__init__.py
@@ -3,8 +3,8 @@
class LM32:
def __init__(self):
- self.ibus = i = wishbone.Master("lm32i")
- self.dbus = d = wishbone.Master("lm32d")
+ self.ibus = i = wishbone.Master()
+ self.dbus = d = wishbone.Master()
self.interrupt = Signal(BV(32))
self.ext_break = Signal()
self._inst = Instance("lm32_top",
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2  milkymist/norflash/__init__.py
@@ -4,7 +4,7 @@
class NorFlash:
def __init__(self, adr_width, rd_timing):
- self.bus = wishbone.Slave("norflash")
+ self.bus = wishbone.Slave()
self.adr = Signal(BV(adr_width-1))
self.d = Signal(BV(16))
self.oe_n = Signal()
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2  milkymist/sram/__init__.py
@@ -3,7 +3,7 @@
class SRAM:
def __init__(self, depth):
- self.bus = wishbone.Slave("sram")
+ self.bus = wishbone.Slave()
self.depth = depth
def get_fragment(self):
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