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Remove explicit bus names

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commit 8a2646a54950248cfe28376ae06cb47f9053e77a 1 parent 28f00c3
Sébastien Bourdeauducq authored January 27, 2012
4  milkymist/lm32/__init__.py
@@ -3,8 +3,8 @@
3 3
 
4 4
 class LM32:
5 5
 	def __init__(self):
6  
-		self.ibus = i = wishbone.Master("lm32i")
7  
-		self.dbus = d = wishbone.Master("lm32d")
  6
+		self.ibus = i = wishbone.Master()
  7
+		self.dbus = d = wishbone.Master()
8 8
 		self.interrupt = Signal(BV(32))
9 9
 		self.ext_break = Signal()
10 10
 		self._inst = Instance("lm32_top",
2  milkymist/norflash/__init__.py
@@ -4,7 +4,7 @@
4 4
 
5 5
 class NorFlash:
6 6
 	def __init__(self, adr_width, rd_timing):
7  
-		self.bus = wishbone.Slave("norflash")
  7
+		self.bus = wishbone.Slave()
8 8
 		self.adr = Signal(BV(adr_width-1))
9 9
 		self.d = Signal(BV(16))
10 10
 		self.oe_n = Signal()
2  milkymist/sram/__init__.py
@@ -3,7 +3,7 @@
3 3
 
4 4
 class SRAM:
5 5
 	def __init__(self, depth):
6  
-		self.bus = wishbone.Slave("sram")
  6
+		self.bus = wishbone.Slave()
7 7
 		self.depth = depth
8 8
 	
9 9
 	def get_fragment(self):

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