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ddrphy: working on hardware, simulation a bit messed up

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commit 8d4a42887ecd5319de1553d9ad6077d2d97ee6ef 1 parent baba267
Sébastien Bourdeauducq authored February 24, 2012
2  software/bios/ddrinit.c
@@ -61,7 +61,6 @@ static void init_sequence(void)
61 61
 	
62 62
 	/* Load Mode Register */
63 63
 	setaddr(0x0132); /* Reset DLL, CL=3, BL=4 */
64  
-	//setaddr(0x0162); /* Reset DLL, CL=2.5, BL=4 */
65 64
 	CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS;
66 65
 	cdelay(200);
67 66
 	
@@ -78,7 +77,6 @@ static void init_sequence(void)
78 77
 	
79 78
 	/* Load Mode Register */
80 79
 	setaddr(0x0032); /* CL=3, BL=4 */
81  
-	//setaddr(0x0062); /* CL=2.5, BL=4 */
82 80
 	CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS;
83 81
 	cdelay(200);
84 82
 }
6  tb/s6ddrphy/tb_s6ddrphy.v
@@ -123,14 +123,13 @@ initial begin
123 123
 `ifdef TEST_WRITE
124 124
 	#13;
125 125
 	dfi_address_p1 <= 13'h0dbe;
126  
-	#12;
127  
-	dfi_address_p1 <= 0;
128 126
 	dfi_wrdata_en_p1 <= 1;
129 127
 	dfi_wrdata_mask_p0 <= 8'h12;
130 128
 	dfi_wrdata_mask_p1 <= 8'h34;
131 129
 	dfi_wrdata_p0 <= 64'hcafebabeabadface;
132 130
 	dfi_wrdata_p1 <= 64'h0123456789abcdef;
133 131
 	#12;
  132
+	dfi_address_p1 <= 0;
134 133
 	dfi_wrdata_en_p1 <= 0;
135 134
 	dfi_wrdata_mask_p0 <= 0;
136 135
 	dfi_wrdata_mask_p1 <= 0;
@@ -142,10 +141,9 @@ initial begin
142 141
 `ifdef TEST_READ
143 142
 	#13;
144 143
 	dfi_address_p0 <= 13'h1234;
145  
-	#12;
146  
-	dfi_address_p0 <= 0;
147 144
 	dfi_rddata_en_p0 <= 1;
148 145
 	#12;
  146
+	dfi_address_p0 <= 0;
149 147
 	dfi_rddata_en_p0 <= 0;
150 148
 	#15.5;
151 149
 	dq_tb <= 32'h12345678;
45  verilog/s6ddrphy/s6ddrphy.v
@@ -218,7 +218,19 @@ endgenerate
218 218
 always @(posedge clk2x_270)
219 219
 	postamble <= drive_dqs;
220 220
 
  221
+reg [NUM_D-1:0] d_dfi_wrdata_p0;
  222
+reg [NUM_D-1:0] d_dfi_wrdata_p1;
  223
+reg [NUM_D/8-1:0] d_dfi_wrdata_mask_p0;
  224
+reg [NUM_D/8-1:0] d_dfi_wrdata_mask_p1;
  225
+always @(posedge sys_clk) begin
  226
+	d_dfi_wrdata_p0 <= dfi_wrdata_p0;
  227
+	d_dfi_wrdata_p1 <= dfi_wrdata_p1;
  228
+	d_dfi_wrdata_mask_p0 <= dfi_wrdata_mask_p0;
  229
+	d_dfi_wrdata_mask_p1 <= dfi_wrdata_mask_p1;
  230
+end
  231
+
221 232
 wire drive_dq;
  233
+wire d_drive_dq;
222 234
 wire [NUM_D/2-1:0] dq_i;
223 235
 wire [NUM_D/2-1:0] dq_o;
224 236
 wire [NUM_D/2-1:0] dq_t;
@@ -239,14 +251,14 @@ generate
239 251
 			.IOCE(clk4x_wr_strb),
240 252
 			.RST(1'b0),
241 253
 			.CLKDIV(sys_clk),
242  
-			.D1(dfi_wrdata_p0[i+NUM_D/2]),
243  
-			.D2(dfi_wrdata_p0[i]),
244  
-			.D3(dfi_wrdata_p1[i+NUM_D/2]),
245  
-			.D4(dfi_wrdata_p1[i]),
  254
+			.D1(d_dfi_wrdata_p0[i]),
  255
+			.D2(d_dfi_wrdata_p1[i+NUM_D/2]),
  256
+			.D3(d_dfi_wrdata_p1[i]),
  257
+			.D4(dfi_wrdata_p0[i+NUM_D/2]),
246 258
 			.TQ(dq_t[i]),
247  
-			.T1(~drive_dq),
248  
-			.T2(~drive_dq),
249  
-			.T3(~drive_dq),
  259
+			.T1(~d_drive_dq),
  260
+			.T2(~d_drive_dq),
  261
+			.T3(~d_drive_dq),
250 262
 			.T4(~drive_dq),
251 263
 			.TRAIN(1'b0),
252 264
 			.TCE(1'b1),
@@ -313,10 +325,10 @@ generate
313 325
 			.IOCE(clk4x_wr_strb),
314 326
 			.RST(1'b0),
315 327
 			.CLKDIV(sys_clk),
316  
-			.D1(dfi_wrdata_mask_p0[i+NUM_D/16]),
317  
-			.D2(dfi_wrdata_mask_p0[i]),
318  
-			.D3(dfi_wrdata_mask_p1[i+NUM_D/16]),
319  
-			.D4(dfi_wrdata_mask_p1[i]),
  328
+			.D1(d_dfi_wrdata_mask_p0[i]),
  329
+			.D2(d_dfi_wrdata_mask_p1[i+NUM_D/16]),
  330
+			.D3(d_dfi_wrdata_mask_p1[i]),
  331
+			.D4(dfi_wrdata_mask_p0[i+NUM_D/16]),
320 332
 			.TQ(),
321 333
 			.T1(),
322 334
 			.T2(),
@@ -344,16 +356,17 @@ reg d_dfi_wrdata_en_p1;
344 356
 always @(posedge sys_clk)
345 357
 	d_dfi_wrdata_en_p1 <= dfi_wrdata_en_p1;
346 358
  
  359
+assign drive_dq = dfi_wrdata_en_p1;
  360
+assign d_drive_dq = d_dfi_wrdata_en_p1;
  361
+ 
347 362
 reg r_dfi_wrdata_en;
348  
-always @(posedge clk2x_270)
349  
-	r_dfi_wrdata_en <= d_dfi_wrdata_en_p1;
350  
-
351 363
 reg r2_dfi_wrdata_en;
352  
-always @(posedge clk2x_270)
  364
+always @(posedge clk2x_270) begin
  365
+	r_dfi_wrdata_en <= d_dfi_wrdata_en_p1;
353 366
 	r2_dfi_wrdata_en <= r_dfi_wrdata_en;
  367
+end
354 368
 
355 369
 assign drive_dqs = r2_dfi_wrdata_en;
356  
-assign drive_dq = d_dfi_wrdata_en_p1;
357 370
 
358 371
 wire rddata_valid;
359 372
 reg [4:0] rddata_sr;

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