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crg: support VGA pixel clock reprogramming

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commit 8fd092ca1273f23d690c33d8791d4ee7cbc1f9bc 1 parent 1e860c7
Sébastien Bourdeauducq authored March 28, 2013
51  milkymist/m1crg/__init__.py
@@ -3,8 +3,9 @@
3 3
 from migen.fhdl.structure import *
4 4
 from migen.fhdl.specials import Instance
5 5
 from migen.fhdl.module import Module
  6
+from migen.bank.description import *
6 7
 
7  
-class M1CRG(Module):
  8
+class M1CRG(Module, AutoReg):
8 9
 	def __init__(self, pads, outfreq1x):
9 10
 		self.clock_domains.cd_sys = ClockDomain()
10 11
 		self.clock_domains.cd_sys2x_270 = ClockDomain()
@@ -17,12 +18,22 @@ def __init__(self, pads, outfreq1x):
17 18
 		self.clk4x_wr_strb = Signal()
18 19
 		self.clk4x_rd_strb = Signal()
19 20
 
  21
+		self._r_cmd_data = RegisterField(10)
  22
+		self._r_send_cmd_data = RegisterRaw()
  23
+		self._r_send_go = RegisterRaw()
  24
+		self._r_status = RegisterField(3, READ_ONLY, WRITE_ONLY)
  25
+
20 26
 		###
21 27
 		
22 28
 		infreq = 50*1000000
23 29
 		ratio = Fraction(outfreq1x)/Fraction(infreq)
24 30
 		in_period = float(Fraction(1000000000)/Fraction(infreq))
25 31
 
  32
+		vga_progdata = Signal()
  33
+		vga_progen = Signal()
  34
+		vga_progdone = Signal()
  35
+		vga_locked = Signal()
  36
+
26 37
 		self.specials += Instance("m1crg",
27 38
 			Instance.Parameter("in_period", in_period),
28 39
 			Instance.Parameter("f_mult", ratio.numerator),
@@ -48,4 +59,40 @@ def __init__(self, pads, outfreq1x):
48 59
 			Instance.Output("ddr_clk_pad_p", pads.ddr_clk_p),
49 60
 			Instance.Output("ddr_clk_pad_n", pads.ddr_clk_n),
50 61
 			Instance.Output("eth_phy_clk_pad", pads.eth_phy_clk),
51  
-			Instance.Output("vga_clk_pad", pads.vga_clk))
  62
+			Instance.Output("vga_clk_pad", pads.vga_clk),
  63
+
  64
+			Instance.Input("vga_progclk", ClockSignal()),
  65
+			Instance.Input("vga_progdata", vga_progdata),
  66
+			Instance.Input("vga_progen", vga_progen),
  67
+			Instance.Output("vga_progdone", vga_progdone),
  68
+			Instance.Output("vga_locked", vga_locked))
  69
+
  70
+		remaining_bits = Signal(max=11)
  71
+		transmitting = Signal()
  72
+		self.comb += transmitting.eq(remaining_bits != 0)
  73
+		sr = Signal(10)
  74
+		self.sync += [
  75
+			If(self._r_send_cmd_data.re,
  76
+				remaining_bits.eq(10),
  77
+				sr.eq(self._r_cmd_data.field.r)
  78
+			).Elif(transmitting,
  79
+				remaining_bits.eq(remaining_bits - 1),
  80
+				sr.eq(sr[1:])
  81
+			)
  82
+		]
  83
+		self.comb += [
  84
+			vga_progdata.eq(transmitting & sr[0]),
  85
+			vga_progen.eq(transmitting | self._r_send_go.re)
  86
+		]
  87
+
  88
+		# enforce gap between commands
  89
+		busy_counter = Signal(max=14)
  90
+		busy = Signal()
  91
+		self.comb += busy.eq(busy_counter != 0)
  92
+		self.sync += If(self._r_send_cmd_data.re,
  93
+				busy_counter.eq(13)
  94
+			).Elif(busy,
  95
+				busy_counter.eq(busy_counter - 1)
  96
+			)
  97
+
  98
+		self.comb += self._r_status.field.w.eq(Cat(busy, vga_progdone, vga_locked))
4  software/include/hw/flags.h
@@ -18,4 +18,8 @@
18 18
 #define MINIMAC_EV_RX1	0x2
19 19
 #define MINIMAC_EV_TX	0x4
20 20
 
  21
+#define CLKGEN_STATUS_BUSY		0x1
  22
+#define CLKGEN_STATUS_PROGDONE	0x2
  23
+#define CLKGEN_STATUS_LOCKED	0x4
  24
+
21 25
 #endif /* __HW_FLAGS_H */
27  top.py
@@ -65,17 +65,18 @@ def __init__(self, platform):
65 65
 class SoC(Module):
66 66
 	csr_base = 0xe0000000
67 67
 	csr_map = {
68  
-		"uart":					0,
69  
-		"dfii":					1,
70  
-		"identifier":			2,
71  
-		"timer0":				3,
72  
-		"minimac":				4,
73  
-		"fb":					5,
74  
-		"asmiprobe":			6,
75  
-		"dvisampler0":			7,
76  
-		"dvisampler0_edid_mem":	8,
77  
-		"dvisampler1":			9,
78  
-		"dvisampler1_edid_mem":	10,
  68
+		"crg":					0,
  69
+		"uart":					1,
  70
+		"dfii":					2,
  71
+		"identifier":			3,
  72
+		"timer0":				4,
  73
+		"minimac":				5,
  74
+		"fb":					6,
  75
+		"asmiprobe":			7,
  76
+		"dvisampler0":			8,
  77
+		"dvisampler0_edid_mem":	9,
  78
+		"dvisampler1":			10,
  79
+		"dvisampler1_edid_mem":	11,
79 80
 	}
80 81
 
81 82
 	interrupt_map = {
@@ -134,6 +135,7 @@ def __init__(self, platform):
134 135
 		#
135 136
 		# CSR
136 137
 		#
  138
+		self.submodules.crg = m1crg.M1CRG(M1ClockPads(platform), clk_freq)
137 139
 		self.submodules.uart = uart.UART(platform.request("serial"), clk_freq, baud=115200)
138 140
 		self.submodules.identifier = identifier.Identifier(0x4D31, version, int(clk_freq))
139 141
 		self.submodules.timer0 = timer.Timer()
@@ -151,11 +153,10 @@ def __init__(self, platform):
151 153
 		#
152 154
 		for k, v in sorted(self.interrupt_map.items(), key=itemgetter(1)):
153 155
 			self.comb += self.cpu.interrupt[v].eq(getattr(self, k).ev.irq)
154  
-		
  156
+
155 157
 		#
156 158
 		# Clocking
157 159
 		#
158  
-		self.submodules.crg = m1crg.M1CRG(M1ClockPads(platform), clk_freq)
159 160
 		self.comb += [
160 161
 			self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
161 162
 			self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb)
22  verilog/m1crg/m1crg.v
@@ -33,7 +33,14 @@ module m1crg #(
33 33
 	
34 34
 	/* VGA clock */
35 35
 	output vga_clk,		/* < buffered, to internal clock network */
36  
-	output vga_clk_pad	/* < forwarded through ODDR2, to I/O */
  36
+	output vga_clk_pad,	/* < forwarded through ODDR2, to I/O */
  37
+
  38
+	/* VGA clock control */
  39
+	input vga_progclk,
  40
+	input vga_progdata,
  41
+	input vga_progen,
  42
+	output vga_progdone,
  43
+	output vga_locked
37 44
 );
38 45
 
39 46
 /*
@@ -257,7 +264,6 @@ assign eth_tx_clk = eth_tx_clk_pad;
257 264
  * VGA clock
258 265
  */
259 266
 
260  
-// TODO: hook up the reprogramming interface
261 267
 DCM_CLKGEN #(
262 268
 	.CLKFXDV_DIVIDE(2),
263 269
 	.CLKFX_DIVIDE(4),
@@ -270,15 +276,15 @@ DCM_CLKGEN #(
270 276
 	.CLKFX(vga_clk),
271 277
 	.CLKFX180(),
272 278
 	.CLKFXDV(),
273  
-	.LOCKED(),
274  
-	.PROGDONE(),
275 279
 	.STATUS(),
276 280
 	.CLKIN(pllout4),
277 281
 	.FREEZEDCM(1'b0),
278  
-	.PROGCLK(1'b0),
279  
-	.PROGDATA(),
280  
-	.PROGEN(1'b0),
281  
-	.RST(1'b0)
  282
+	.PROGCLK(vga_progclk),
  283
+	.PROGDATA(vga_progdata),
  284
+	.PROGEN(vga_progen),
  285
+	.PROGDONE(vga_progdone),
  286
+	.LOCKED(vga_locked),
  287
+	.RST(~pll_lckd)
282 288
 );
283 289
 
284 290
 ODDR2 #(

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