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framebuffer: use new flow API

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commit 950d3a44694dc0e47baa90d7dda2ea1cb1c435b9 1 parent 3be20f6
Sébastien Bourdeauducq authored April 10, 2013

Showing 1 changed file with 30 additions and 31 deletions. Show diff stats Hide diff stats

  1. 61  milkymist/framebuffer/__init__.py
61  milkymist/framebuffer/__init__.py
@@ -55,10 +55,9 @@ def __init__(self, asmi_bits, length_bits, alignment_bits):
55 55
 		]
56 56
 		spi.SingleGenerator.__init__(self, layout, spi.MODE_CONTINUOUS)
57 57
 
58  
-class VTG(Module, Actor):
  58
+class VTG(Module):
59 59
 	def __init__(self):
60  
-		Actor.__init__(self,
61  
-			("timing", Sink, [
  60
+		self.timing = Sink([
62 61
 				("hres", _hbits),
63 62
 				("hsync_start", _hbits),
64 63
 				("hsync_end", _hbits),
@@ -66,10 +65,10 @@ def __init__(self):
66 65
 				("vres", _vbits),
67 66
 				("vsync_start", _vbits),
68 67
 				("vsync_end", _vbits),
69  
-				("vscan", _vbits)]),
70  
-			("pixels", Sink, _pixel_layout),
71  
-			("dac", Source, _dac_layout)
72  
-		)
  68
+				("vscan", _vbits)])
  69
+		self.pixels = Sink(_pixel_layout)
  70
+		self.dac = Source(_dac_layout)
  71
+		self.busy = Signal()
73 72
 
74 73
 		hactive = Signal()
75 74
 		vactive = Signal()
@@ -83,29 +82,30 @@ def __init__(self):
83 82
 		self.comb += [
84 83
 			active.eq(hactive & vactive),
85 84
 			If(active,
86  
-				[getattr(getattr(self.token("dac"), p), c).eq(getattr(getattr(self.token("pixels"), p), c)[skip:])
  85
+				[getattr(getattr(self.dac.payload, p), c).eq(getattr(getattr(self.pixels.payload, p), c)[skip:])
87 86
 					for p in ["p0", "p1"] for c in ["r", "g", "b"]]
88 87
 			),
89 88
 			
90  
-			generate_en.eq(self.endpoints["timing"].stb & (~active | self.endpoints["pixels"].stb)),
91  
-			self.endpoints["pixels"].ack.eq(self.endpoints["dac"].ack & active),
92  
-			self.endpoints["dac"].stb.eq(generate_en)
  89
+			generate_en.eq(self.timing.stb & (~active | self.pixels.stb)),
  90
+			self.pixels.ack.eq(self.dac.ack & active),
  91
+			self.dac.stb.eq(generate_en),
  92
+			self.busy.eq(generate_en)
93 93
 		]
94  
-		tp = self.token("timing")
  94
+		tp = self.timing.payload
95 95
 		self.sync += [
96  
-			self.endpoints["timing"].ack.eq(0),
97  
-			If(generate_en & self.endpoints["dac"].ack,
  96
+			self.timing.ack.eq(0),
  97
+			If(generate_en & self.dac.ack,
98 98
 				hcounter.eq(hcounter + 1),
99 99
 			
100 100
 				If(hcounter == 0, hactive.eq(1)),
101 101
 				If(hcounter == tp.hres, hactive.eq(0)),
102  
-				If(hcounter == tp.hsync_start, self.token("dac").hsync.eq(1)),
103  
-				If(hcounter == tp.hsync_end, self.token("dac").hsync.eq(0)),
  102
+				If(hcounter == tp.hsync_start, self.dac.payload.hsync.eq(1)),
  103
+				If(hcounter == tp.hsync_end, self.dac.payload.hsync.eq(0)),
104 104
 				If(hcounter == tp.hscan,
105 105
 					hcounter.eq(0),
106 106
 					If(vcounter == tp.vscan,
107 107
 						vcounter.eq(0),
108  
-						self.endpoints["timing"].ack.eq(1)
  108
+						self.timing.ack.eq(1)
109 109
 					).Else(
110 110
 						vcounter.eq(vcounter + 1)
111 111
 					)
@@ -113,14 +113,15 @@ def __init__(self):
113 113
 				
114 114
 				If(vcounter == 0, vactive.eq(1)),
115 115
 				If(vcounter == tp.vres, vactive.eq(0)),
116  
-				If(vcounter == tp.vsync_start, self.token("dac").vsync.eq(1)),
117  
-				If(vcounter == tp.vsync_end, self.token("dac").vsync.eq(0))
  116
+				If(vcounter == tp.vsync_start, self.dac.payload.vsync.eq(1)),
  117
+				If(vcounter == tp.vsync_end, self.dac.payload.vsync.eq(0))
118 118
 			)
119 119
 		]
120 120
 
121  
-class FIFO(Module, Actor):
  121
+class FIFO(Module):
122 122
 	def __init__(self):
123  
-		Actor.__init__(self, ("dac", Sink, _dac_layout))
  123
+		self.dac = Sink(_dac_layout)
  124
+		self.busy = Signal()
124 125
 		
125 126
 		self.vga_hsync_n = Signal()
126 127
 		self.vga_vsync_n = Signal()
@@ -151,13 +152,13 @@ def __init__(self):
151 152
 			Instance.Input("clk_write", ClockSignal()),
152 153
 			
153 154
 			Instance.Input("rst", 0))
154  
-		fifo_in = self.token("dac")
  155
+		fifo_in = self.dac.payload
155 156
 		fifo_out = Record(_dac_layout)
156 157
 		self.comb += [
157  
-			self.endpoints["dac"].ack.eq(~fifo_full),
158  
-			fifo_write_en.eq(self.endpoints["dac"].stb),
159  
-			fifo_data_in.eq(Cat(*fifo_in.flatten())),
160  
-			Cat(*fifo_out.flatten()).eq(fifo_data_out),
  158
+			self.dac.ack.eq(~fifo_full),
  159
+			fifo_write_en.eq(self.dac.stb),
  160
+			fifo_data_in.eq(fifo_in.raw_bits()),
  161
+			fifo_out.raw_bits().eq(fifo_data_out),
161 162
 			self.busy.eq(0)
162 163
 		]
163 164
 
@@ -193,7 +194,7 @@ def __init__(self, pads, asmiport, simulation=False):
193 194
 		pack_factor = asmiport.hub.dw//(2*_bpp)
194 195
 		packed_pixels = structuring.pack_layout(_pixel_layout, pack_factor)
195 196
 		
196  
-		fi = _FrameInitiator(asmi_bits, length_bits, alignment_bits)
  197
+		self._fi = fi = _FrameInitiator(asmi_bits, length_bits, alignment_bits)
197 198
 		adrloop = misc.IntSequence(length_bits, asmi_bits)
198 199
 		adrbuffer = AbstractActor(plumbing.Buffer)
199 200
 		dma = dma_asmi.Reader(asmiport)
@@ -218,9 +219,7 @@ def __init__(self, pads, asmiport, simulation=False):
218 219
 			"hres", "hsync_start", "hsync_end", "hscan", 
219 220
 			"vres", "vsync_start", "vsync_end", "vscan"])
220 221
 		g.add_connection(vtg, fifo)
221  
-		self.submodules._comp_actor = CompositeActor(g, debugger=False)
222  
-		
223  
-		self._csrs = fi.get_csrs() + self._comp_actor.get_csrs()
  222
+		self.submodules._comp_actor = CompositeActor(g)
224 223
 		
225 224
 		# Drive pads
226 225
 		if not simulation:
@@ -234,4 +233,4 @@ def __init__(self, pads, asmiport, simulation=False):
234 233
 		self.comb += pads.psave_n.eq(1)
235 234
 
236 235
 	def get_csrs(self):
237  
-		return self._csrs
  236
+		return self._fi.get_csrs()

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