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Memory map

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commit 9b9a510525534bfbd5beff8090569ad824e81436 1 parent 17cd8dd
Sébastien Bourdeauducq authored February 05, 2012

Showing 1 changed file with 16 additions and 2 deletions. Show diff stats Hide diff stats

  1. 18  top.py
18  top.py
@@ -17,11 +17,25 @@ def get():
17 17
 	norflash0 = norflash.NorFlash(25, 12)
18 18
 	sram0 = sram.SRAM(sram_size//4)
19 19
 	wishbone2csr0 = wishbone2csr.WB2CSR()
  20
+	
  21
+	# norflash     0x00000000 (shadow @0x80000000)
  22
+	# SRAM/debug   0x10000000 (shadow @0x90000000)
  23
+	# USB          0x20000000 (shadow @0xa0000000)
  24
+	# Ethernet     0x30000000 (shadow @0xb0000000)
  25
+	# SDRAM        0x40000000 (shadow @0xc0000000)
  26
+	# CSR bridge   0x60000000 (shadow @0xe0000000)	
20 27
 	wishbonecon0 = wishbone.InterconnectShared(
21  
-		[cpu0.ibus, cpu0.dbus],
22  
-		[(0, norflash0.bus), (1, sram0.bus), (3, wishbone2csr0.wishbone)],
  28
+		[
  29
+			cpu0.ibus,
  30
+			cpu0.dbus
  31
+		], [
  32
+			(binc("000"), norflash0.bus),
  33
+			(binc("001"), sram0.bus),
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+			(binc("11"), wishbone2csr0.wishbone)
  35
+		],
23 36
 		register=True,
24 37
 		offset=1)
  38
+	
25 39
 	uart0 = uart.UART(0, clk_freq, baud=115200)
26 40
 	csrcon0 = csr.Interconnect(wishbone2csr0.csr, [uart0.bank.interface])
27 41
 	

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