Skip to content
Permalink
Browse files
Use automatic register naming
  • Loading branch information
Sebastien Bourdeauducq committed Mar 12, 2013
1 parent a9b7235 commit a23df42a7a0e58e09c96084d140f94d25df330c4
@@ -9,12 +9,10 @@ def __init__(self, hub, trace_depth=16):
assert(trace_depth < 256)
assert(slot_count < 256)

self._slot_count = RegisterField("slot_count", 8, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
self._trace_depth = RegisterField("trace_depth", 8, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
self._slot_status = [RegisterField("slot_status" + str(i), 2, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
for i in range(slot_count)]
self._trace = [RegisterField("trace" + str(i), 8, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
for i in range(trace_depth)]
self._slot_count = RegisterField(8, READ_ONLY, WRITE_ONLY)
self._trace_depth = RegisterField(8, READ_ONLY, WRITE_ONLY)
self._slot_status = [RegisterField(2, READ_ONLY, WRITE_ONLY, name="slot_status" + str(i)) for i in range(slot_count)]
self._trace = [RegisterField(8, READ_ONLY, WRITE_ONLY, name="trace" + str(i)) for i in range(trace_depth)]

###

@@ -5,21 +5,20 @@

class PhaseInjector(Module, AutoReg):
def __init__(self, phase):
self._cs = Field("cs", 1, WRITE_ONLY, READ_ONLY)
self._we = Field("we", 1, WRITE_ONLY, READ_ONLY)
self._cas = Field("cas", 1, WRITE_ONLY, READ_ONLY)
self._ras = Field("ras", 1, WRITE_ONLY, READ_ONLY)
self._wren = Field("wren", 1, WRITE_ONLY, READ_ONLY)
self._rden = Field("rden", 1, WRITE_ONLY, READ_ONLY)
self._command = RegisterFields("command",
[self._cs, self._we, self._cas, self._ras, self._wren, self._rden])
self._command_issue = RegisterRaw("command_issue")
self._cs = Field(1, WRITE_ONLY, READ_ONLY)
self._we = Field(1, WRITE_ONLY, READ_ONLY)
self._cas = Field(1, WRITE_ONLY, READ_ONLY)
self._ras = Field(1, WRITE_ONLY, READ_ONLY)
self._wren = Field(1, WRITE_ONLY, READ_ONLY)
self._rden = Field(1, WRITE_ONLY, READ_ONLY)
self._command = RegisterFields(self._cs, self._we, self._cas, self._ras, self._wren, self._rden)
self._command_issue = RegisterRaw()

self._address = RegisterField("address", len(phase.address))
self._baddress = RegisterField("baddress", len(phase.bank))
self._address = RegisterField(len(phase.address))
self._baddress = RegisterField(len(phase.bank))

self._wrdata = RegisterField("wrdata", len(phase.wrdata))
self._rddata = RegisterField("rddata", len(phase.rddata), READ_ONLY, WRITE_ONLY)
self._wrdata = RegisterField(len(phase.wrdata))
self._rddata = RegisterField(len(phase.rddata), READ_ONLY, WRITE_ONLY)

###

@@ -50,9 +49,9 @@ def __init__(self, a, ba, d, nphases=1):
self.slave = dfi.Interface(a, ba, d, nphases)
self.master = dfi.Interface(a, ba, d, nphases)

self._sel = Field("sel")
self._cke = Field("cke")
self._control = RegisterFields("control", [self._sel, self._cke])
self._sel = Field()
self._cke = Field()
self._control = RegisterFields(self._sel, self._cke)

for n, phase in enumerate(inti.phases):
setattr(self.submodules, "pi" + str(n), PhaseInjector(phase))
@@ -6,7 +6,6 @@
from migen.flow.transactions import *
from migen.flow import plumbing
from migen.actorlib import misc, dma_asmi, structuring, sim, spi
from migen.bank.description import *

_hbits = 11
_vbits = 11
@@ -17,9 +17,9 @@ def encode_version(version):

class Identifier(Module, AutoReg):
def __init__(self, sysid, version, frequency):
self._r_sysid = RegisterField("sysid", 16, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
self._r_version = RegisterField("version", 16, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
self._r_frequency = RegisterField("frequency", 32, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
self._r_sysid = RegisterField(16, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
self._r_version = RegisterField(16, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
self._r_frequency = RegisterField(32, access_bus=READ_ONLY, access_dev=WRITE_ONLY)

###

@@ -23,11 +23,11 @@ def __init__(self):
self.phy_rst_n = Signal()

# CPU interface
self._phy_reset = RegisterField("phy_reset", reset=1)
self._rx_count_0 = RegisterField("rx_count_0", _count_width, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
self._rx_count_1 = RegisterField("rx_count_1", _count_width, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
self._tx_count = RegisterField("tx_count", _count_width, access_dev=READ_WRITE)
self._tx_start = RegisterRaw("tx_start")
self._phy_reset = RegisterField(reset=1)
self._rx_count_0 = RegisterField(_count_width, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
self._rx_count_1 = RegisterField(_count_width, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
self._tx_count = RegisterField(_count_width, access_dev=READ_WRITE)
self._tx_start = RegisterRaw()

self.submodules.ev = EventManager()
self.ev.rx0 = EventSourcePulse()
@@ -5,9 +5,9 @@

class Timer(Module, AutoReg):
def __init__(self, width=32):
self._en = RegisterField("en")
self._value = RegisterField("value", width, access_dev=READ_WRITE)
self._reload = RegisterField("reload", width)
self._en = RegisterField()
self._value = RegisterField(width, access_dev=READ_WRITE)
self._reload = RegisterField(width)

self.submodules.ev = EventManager()
self.ev.zero = EventSourceLevel()
@@ -6,8 +6,8 @@

class UART(Module, AutoReg):
def __init__(self, clk_freq, baud=115200):
self._rxtx = RegisterRaw("rxtx", 8)
self._divisor = RegisterField("divisor", 16, reset=int(clk_freq/baud/16))
self._rxtx = RegisterRaw(8)
self._divisor = RegisterField(16, reset=int(clk_freq/baud/16))

self.submodules.ev = EventManager()
self.ev.tx = EventSourceLevel()

0 comments on commit a23df42

Please sign in to comment.