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framebuffer: frame initiator

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commit a52c3135c1a4cff9b63a7efa6c5962d605dde165 1 parent 3a02524
Sébastien Bourdeauducq authored
81  milkymist/framebuffer/__init__.py
... ...
@@ -1,11 +1,83 @@
1 1
 from migen.fhdl.structure import *
  2
+from migen.flow.actor import *
  3
+from migen.flow.network import *
  4
+from migen.bank.description import *
  5
+from migen.bank import csrgen
  6
+
  7
+_hbits = 11
  8
+_vbits = 11
  9
+
  10
+class _FrameInitiator(Actor):
  11
+	def __init__(self, asmi_bits, alignment_bits):
  12
+		self._alignment_bits = alignment_bits
  13
+		length_bits = _hbits + _vbits + 2 - alignment_bits
  14
+		
  15
+		self._enable = RegisterField("enable")
  16
+		
  17
+		self._hres = RegisterField("hres", _hbits, reset=640)
  18
+		self._hsync_start = RegisterField("hsync_start", _hbits, reset=656)
  19
+		self._hsync_end = RegisterField("hsync_end", _hbits, reset=752)
  20
+		self._hscan = RegisterField("hscan", _hbits, reset=799)
  21
+		
  22
+		self._vres = RegisterField("vres", _vbits, reset=480)
  23
+		self._vsync_start = RegisterField("vsync_start", _vbits, reset=492)
  24
+		self._vsync_end = RegisterField("vsync_end", _vbits, reset=494)
  25
+		self._vscan = RegisterField("vscan", _vbits, reset=524)
  26
+		
  27
+		self._base = RegisterField("base", asmi_bits + self._alignment_bits)
  28
+		self._length = RegisterField("length", length_bits + self._alignment_bits)
  29
+		
  30
+		layout = [
  31
+			("hres", BV(_hbits)),
  32
+			("hsync_start", BV(_hbits)),
  33
+			("hsync_end", BV(_hbits)),
  34
+			("hscan", BV(_hbits)),
  35
+			("vres", BV(_vbits)),
  36
+			("vsync_start", BV(_vbits)),
  37
+			("vsync_end", BV(_vbits)),
  38
+			("vscan", BV(_vbits)),
  39
+			("base", BV(asmi_bits)),
  40
+			("length", BV(length_bits))
  41
+		]
  42
+		super().__init__(("frame", Source, layout))
  43
+		
  44
+	def get_registers(self):
  45
+		return [self._enable,
  46
+			self._hres, self._hsync_start, self._hsync_end, self._hscan,
  47
+			self._vres, self._vsync_start, self._vsync_end, self._vscan,
  48
+			self._base, self._length]
  49
+		
  50
+	def get_fragment(self):
  51
+		# TODO: make address updates atomic
  52
+		token = self.token("frame")
  53
+		comb = [
  54
+			self.endpoints["frame"].stb.eq(self._enable.field.r),
  55
+			token.hres.eq(self._hres.field.r),
  56
+			token.hsync_start.eq(self._hsync_start.field.r),
  57
+			token.hsync_end.eq(self._hsync_end.field.r),
  58
+			token.hscan.eq(self._hscan.field.r),
  59
+			token.vres.eq(self._vres.field.r),
  60
+			token.vsync_start.eq(self._vsync_start.field.r),
  61
+			token.vsync_end.eq(self._vsync_end.field.r),
  62
+			token.vscan.eq(self._vscan.field.r),
  63
+			token.base.eq(self._base.field.r[self._alignment_bits:]),
  64
+			token.length.eq(self._length.field.r[self._alignment_bits:])
  65
+		]
  66
+		return Fragment(comb)
2 67
 
3 68
 class Framebuffer:
4  
-	def __init__(self, csr_address, asmiport):
  69
+	def __init__(self, address, asmiport):
  70
+		asmi_bits = asmiport.hub.aw
  71
+		alignment_bits = asmiport.hub.dw//8
  72
+		
  73
+		fi = _FrameInitiator(asmi_bits, alignment_bits)
  74
+		
  75
+		self.bank = csrgen.Bank(fi.get_registers(), address=address)
  76
+		
5 77
 		# VGA clock input
6 78
 		self.vga_clk = Signal()
7 79
 		
8  
-		# pads
  80
+		# Pads
9 81
 		self.vga_psave_n = Signal()
10 82
 		self.vga_hsync_n = Signal()
11 83
 		self.vga_vsync_n = Signal()
@@ -16,4 +88,9 @@ def __init__(self, csr_address, asmiport):
16 88
 		self.vga_b = Signal(BV(8))
17 89
 
18 90
 	def get_fragment(self):
  91
+		comb = [
  92
+			self.vga_sync_n.eq(0),
  93
+			self.vga_psave_n.eq(1),
  94
+			self.vga_blank_n.eq(1)
  95
+		]
19 96
 		return Fragment()
2  top.py
@@ -131,7 +131,7 @@ def get():
131 131
 		identifier0.bank.interface,
132 132
 		timer0.bank.interface,
133 133
 		minimac0.bank.interface,
134  
-		#fb0.bank.interface
  134
+		fb0.bank.interface
135 135
 	])
136 136
 	
137 137
 	#

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