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memtest: LFSR

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commit a7a7cc0b954f2301a7aa98e4e1911b3f83a0afba 1 parent 26ff6f2
@sbourdeauducq sbourdeauducq authored
Showing with 30 additions and 0 deletions.
  1. +30 −0 milkymist/memtest/__init__.py
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30 milkymist/memtest/__init__.py
@@ -0,0 +1,30 @@
+from migen.fhdl.std import *
+from migen.genlib.misc import optree
+from migen.fhdl import verilog
+
+class LFSR(Module):
+ def __init__(self, n_out, n_state=31, taps=[27, 30]):
+ self.ce = Signal()
+ self.o = Signal(n_out)
+
+ ###
+
+ state = Signal(n_state)
+ curval = [state[i] for i in range(n_state)]
+ curval += [0]*(n_out - n_state)
+ for i in range(n_out):
+ nv = optree("^", [curval[tap] for tap in taps])
+ curval.insert(0, nv)
+ curval.pop()
+
+ self.sync += If(self.ce,
+ state.eq(Cat(*curval[:n_state])),
+ self.o.eq(Cat(*curval))
+ )
+
+def _printcode():
+ dut = LFSR(3, 4, [3, 2])
+ print(verilog.convert(dut, ios={dut.ce, dut.o}))
+
+if __name__ == "__main__":
+ _printcode()
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