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memtest: LFSR

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commit a7a7cc0b954f2301a7aa98e4e1911b3f83a0afba 1 parent 26ff6f2
Sébastien Bourdeauducq authored July 10, 2013

Showing 1 changed file with 30 additions and 0 deletions. Show diff stats Hide diff stats

  1. 30  milkymist/memtest/__init__.py
30  milkymist/memtest/__init__.py
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+from migen.fhdl.std import *
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+from migen.genlib.misc import optree
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+from migen.fhdl import verilog
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+
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+class LFSR(Module):
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+	def __init__(self, n_out, n_state=31, taps=[27, 30]):
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+		self.ce = Signal()
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+		self.o = Signal(n_out)
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+
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+		###
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+
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+		state = Signal(n_state)
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+		curval = [state[i] for i in range(n_state)]
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+		curval += [0]*(n_out - n_state)
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+		for i in range(n_out):
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+			nv = optree("^", [curval[tap] for tap in taps])
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+			curval.insert(0, nv)
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+			curval.pop()
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+
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+		self.sync += If(self.ce,
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+				state.eq(Cat(*curval[:n_state])),
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+				self.o.eq(Cat(*curval))
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+			)
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+
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+def _printcode():
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+	dut = LFSR(3, 4, [3, 2])
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+	print(verilog.convert(dut, ios={dut.ce, dut.o}))
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+
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+if __name__ == "__main__":
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+	_printcode()

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