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framebuffer: VTG and FIFO skeleton

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commit acdd34e4aebbd0751493909894c24b8eb4c0520e 1 parent ccbd5e8
Sébastien Bourdeauducq authored June 29, 2012

Showing 1 changed file with 64 additions and 15 deletions. Show diff stats Hide diff stats

  1. 79  milkymist/framebuffer/__init__.py
79  milkymist/framebuffer/__init__.py
@@ -9,6 +9,24 @@
9 9
 _hbits = 11
10 10
 _vbits = 11
11 11
 
  12
+_bpp = 32
  13
+_bpc = 10
  14
+_pixel_layout = [
  15
+	("b", BV(_bpc)),
  16
+	("g", BV(_bpc)),
  17
+	("r", BV(_bpc)),
  18
+	("pad", BV(_bpp-3*_bpc))
  19
+]
  20
+
  21
+_bpc_dac = 8
  22
+_dac_layout = [
  23
+	("hsync", BV(1)),
  24
+	("vsync", BV(1)),
  25
+	("b", BV(_bpc_dac)),
  26
+	("g", BV(_bpc_dac)),
  27
+	("r", BV(_bpc_dac))
  28
+]
  29
+
12 30
 class _FrameInitiator(Actor):
13 31
 	def __init__(self, asmi_bits, length_bits, alignment_bits):
14 32
 		self._alignment_bits = alignment_bits
@@ -52,6 +70,7 @@ def get_fragment(self):
52 70
 		# TODO: make address updates atomic
53 71
 		token = self.token("frame")
54 72
 		comb = [
  73
+			self.busy.eq(0),
55 74
 			self.endpoints["frame"].stb.eq(self._enable.field.r),
56 75
 			token.hres.eq(self._hres.field.r),
57 76
 			token.hsync_start.eq(self._hsync_start.field.r),
@@ -66,14 +85,38 @@ def get_fragment(self):
66 85
 		]
67 86
 		return Fragment(comb)
68 87
 
69  
-_bpp = 32
70  
-_bpc = 10
71  
-_pixel_layout = [
72  
-	("b", BV(_bpc)),
73  
-	("g", BV(_bpc)),
74  
-	("r", BV(_bpc)),
75  
-	("pad", BV(_bpp-3*_bpc))
76  
-]
  88
+class VTG(Actor):
  89
+	def __init__(self):
  90
+		super().__init__(
  91
+			("timing", Sink, [
  92
+				("hres", BV(_hbits)),
  93
+				("hsync_start", BV(_hbits)),
  94
+				("hsync_end", BV(_hbits)),
  95
+				("hscan", BV(_hbits)),
  96
+				("vres", BV(_vbits)),
  97
+				("vsync_start", BV(_vbits)),
  98
+				("vsync_end", BV(_vbits)),
  99
+				("vscan", BV(_vbits))]),
  100
+			("pixels", Sink, _pixel_layout),
  101
+			("dac", Source, _dac_layout)
  102
+		)
  103
+	
  104
+	def get_fragment(self):
  105
+		return Fragment() # TODO
  106
+
  107
+class FIFO(Actor):
  108
+	def __init__(self):
  109
+		super().__init__(("dac", Sink, _dac_layout))
  110
+		
  111
+		self.vga_clk = Signal()
  112
+		self.vga_hsync_n = Signal()
  113
+		self.vga_vsync_n = Signal()
  114
+		self.vga_r = Signal(BV(8))
  115
+		self.vga_g = Signal(BV(8))
  116
+		self.vga_b = Signal(BV(8))
  117
+	
  118
+	def get_fragment(self):
  119
+		return Fragment() # TODO
77 120
 
78 121
 class Framebuffer:
79 122
 	def __init__(self, address, asmiport):
@@ -90,7 +133,8 @@ def __init__(self, address, asmiport):
90 133
 		dma = ActorNode(dma_asmi.SequentialReader(asmiport))
91 134
 		cast = ActorNode(structuring.Cast(asmiport.hub.dw, packed_pixels))
92 135
 		unpack = ActorNode(structuring.Unpack(pack_factor, _pixel_layout))
93  
-		# TODO: VTG
  136
+		vtg = ActorNode(VTG())
  137
+		fifo = ActorNode(FIFO())
94 138
 		
95 139
 		g = DataFlowGraph()
96 140
 		g.add_connection(fi, adrloop, source_subr=["length"])
@@ -100,22 +144,27 @@ def __init__(self, address, asmiport):
100 144
 		g.add_connection(adrbuffer, dma)
101 145
 		g.add_connection(dma, cast)
102 146
 		g.add_connection(cast, unpack)
  147
+		g.add_connection(unpack, vtg, sink_ep="pixels")
  148
+		g.add_connection(fi, vtg, sink_ep="timing", source_subr=[
  149
+			"hres", "hsync_start", "hsync_end", "hscan", 
  150
+			"vres", "vsync_start", "vsync_end", "vscan"])
  151
+		g.add_connection(vtg, fifo)
103 152
 		self._comp_actor = CompositeActor(g)
104 153
 		
105 154
 		self.bank = csrgen.Bank(fi.actor.get_registers(), address=address)
106 155
 		
107 156
 		# VGA clock input
108  
-		self.vga_clk = Signal()
  157
+		self.vga_clk = fifo.actor.vga_clk
109 158
 		
110 159
 		# Pads
111 160
 		self.vga_psave_n = Signal()
112  
-		self.vga_hsync_n = Signal()
113  
-		self.vga_vsync_n = Signal()
  161
+		self.vga_hsync_n = fifo.actor.vga_hsync_n
  162
+		self.vga_vsync_n = fifo.actor.vga_vsync_n
114 163
 		self.vga_sync_n = Signal()
115 164
 		self.vga_blank_n = Signal()
116  
-		self.vga_r = Signal(BV(8))
117  
-		self.vga_g = Signal(BV(8))
118  
-		self.vga_b = Signal(BV(8))
  165
+		self.vga_r = fifo.actor.vga_r
  166
+		self.vga_g = fifo.actor.vga_g
  167
+		self.vga_b = fifo.actor.vga_b
119 168
 
120 169
 	def get_fragment(self):
121 170
 		comb = [

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