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asmicon: bank machine (untested)

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commit b1eb919ad21ad8fcd513c46b678d93bcd28b4b13 1 parent 7c37788
Sébastien Bourdeauducq authored March 18, 2012
12  milkymist/asmicon/__init__.py
@@ -6,9 +6,7 @@
6 6
 from milkymist.asmicon.multiplexer import *
7 7
 
8 8
 class PhySettings:
9  
-	def __init__(self, dfi_a, dfi_d, nphases, rdphase, wrphase):
10  
-		# NB: dfi_ba is obtained from GeomSettings.bank_a
11  
-		self.dfi_a = dfi_a
  9
+	def __init__(self, dfi_d, nphases, rdphase, wrphase):
12 10
 		self.dfi_d = dfi_d
13 11
 		self.nphases = nphases
14 12
 		self.rdphase = rdphase
@@ -19,10 +17,12 @@ def __init__(self, bank_a, row_a, col_a):
19 17
 		self.bank_a = bank_a
20 18
 		self.row_a = row_a
21 19
 		self.col_a = col_a
  20
+		self.mux_a = max(row_a, col_a)
22 21
 
23 22
 class TimingSettings:
24  
-	def __init__(self, tRP, tREFI, tRFC):
  23
+	def __init__(self, tRP, tRCD, tREFI, tRFC):
25 24
 		self.tRP = tRP
  25
+		self.tRCD = tRCD
26 26
 		self.tREFI = tREFI
27 27
 		self.tRFC = tRFC
28 28
 
@@ -33,7 +33,7 @@ def __init__(self, phy_settings, geom_settings, timing_settings, time=0):
33 33
 		self.timing_settings = timing_settings
34 34
 		self.finalized = False
35 35
 		
36  
-		self.dfi = dfi.Interface(self.phy_settings.dfi_a,
  36
+		self.dfi = dfi.Interface(self.geom_settings.mux_a,
37 37
 			self.geom_settings.bank_a,
38 38
 			self.phy_settings.dfi_d,
39 39
 			self.phy_settings.nphases)
@@ -49,7 +49,7 @@ def finalize(self):
49 49
 		self.finalized = True
50 50
 		self.hub.finalize()
51 51
 		slots = self.hub.get_slots()
52  
-		self.refresher = Refresher(self.phy_settings.dfi_a, self.geom_settings.bank_a,
  52
+		self.refresher = Refresher(self.geom_settings.mux_a, self.geom_settings.bank_a,
53 53
 			self.timing_settings.tRP, self.timing_settings.tREFI, self.timing_settings.tRFC)
54 54
 		self.bank_machines = [BankMachine(self.geom_settings, self.timing_settings, self.address_align, i, slots) for i in range(2**self.geom_settings.bank_a)]
55 55
 		self.multiplexer = Multiplexer(self.phy_settings, self.geom_settings, self.timing_settings,
242  milkymist/asmicon/bankmachine.py
... ...
@@ -1,8 +1,246 @@
1 1
 from migen.fhdl.structure import *
  2
+from migen.bus.asmibus import *
  3
+from migen.corelogic.roundrobin import *
  4
+from migen.corelogic.fsm import FSM
  5
+from migen.corelogic.misc import multimux, optree
2 6
 
  7
+from milkymist.asmicon.multiplexer import *
  8
+
  9
+# Row:Bank:Col address mapping
  10
+class _AddressSlicer:
  11
+	def __init__(self, geom_settings, address_align):
  12
+		self.geom_settings = geom_settings
  13
+		self.address_align = address_align
  14
+		
  15
+		self._b1 = self.geom_settings.col_a - self.address_align
  16
+		self._b2 = self._b1 + self.geom_settings.row_a
  17
+	
  18
+	def bank(self, address):
  19
+		return address[self._b2:]
  20
+	
  21
+	def row(self, address):
  22
+		return address[self._b1:self._b2]
  23
+	
  24
+	def col(self, address):
  25
+		return Cat(Constant(0, BV(self.address_align)), address[:self._b1])
  26
+
  27
+class _Selector:
  28
+	def __init__(self, slicer, bankn, slots):
  29
+		self.slicer = slicer
  30
+		self.bankn = bankn
  31
+		self.slots = slots
  32
+		
  33
+		self.nslots = len(self.slots)
  34
+		self.stb = Signal()
  35
+		self.ack = Signal()
  36
+		self.tag = Signal(BV(bits_for(self.nslots-1)))
  37
+		self.adr = Signal(self.slots[0].adr.bv)
  38
+		self.we = Signal()
  39
+		
  40
+	def get_fragment(self):
  41
+		comb = []
  42
+		sync = []
  43
+
  44
+		# List outstanding requests for our bank
  45
+		outstandings = []
  46
+		for slot in self.slots:
  47
+			outstanding = Signal()
  48
+			comb.append(outstanding.eq(
  49
+				self.slicer.bank(slot.adr) == self.bankn & \
  50
+				slot.state == SLOT_PENDING
  51
+			))
  52
+			outstandings.append(outstanding)
  53
+		
  54
+		# Row tracking
  55
+		openrow_r = Signal(BV(self.slicer.geom_settings.row_a))
  56
+		openrow_n = Signal(BV(self.slicer.geom_settings.row_a))
  57
+		openrow = Signal(BV(self.slicer.geom_settings.row_a))
  58
+		comb += [
  59
+			openrow_n.eq(self.slicer.row(self.adr)),
  60
+			If(self.stb,
  61
+				openrow.eq(openrow_n)
  62
+			).Else(
  63
+				openrow.eq(openrow_r)
  64
+			)
  65
+		]
  66
+		sync += [
  67
+			If(self.stb & self.ack,
  68
+				openrow_r.eq(openrow_n)
  69
+			)
  70
+		]
  71
+		hits = []
  72
+		for slot in self.slots:
  73
+			hit = Signal()
  74
+			comb.append(hit.eq(self.slicer.row(slot.adr) == openrow))
  75
+			hits.append(hit)
  76
+		
  77
+		# Determine best request
  78
+		rr = RoundRobin(self.nslots, SP_CE)
  79
+		has_hit = Signal()
  80
+		comb.append(has_hit.eq(optree("|", hits)))
  81
+		
  82
+		best_hit = [rr.request[i].eq(hit & os)
  83
+			for i, (hit, os) in enumerate(zip(hits, outstandings))]
  84
+		best_fallback = [rr.request[i].eq(os)
  85
+			for i, os in enumerate(outstandings)]
  86
+		select_stmt = If(has_hit,
  87
+				*best_hit
  88
+			).Else(
  89
+				*best_fallback
  90
+			)
  91
+		
  92
+		if self.slots[0].time:
  93
+			# Implement anti-starvation timer
  94
+			has_mature = Signal()
  95
+			comb.append(has_mature.eq(optree("|", [slot.mature for slot in self.slots])))
  96
+			best_mature = [rr.request[i].eq(slot.mature & os)
  97
+				for i, (slot, os) in enumerate(zip(self.slots, outstandings))]
  98
+			select_stmt = If(has_mature, *best_mature).Else(select_stmt)
  99
+		comb.append(select_stmt)
  100
+		
  101
+		# Multiplex
  102
+		state = Signal(BV(2))
  103
+		mux_outputs = [state, self.adr, self.we]
  104
+		mux_inputs = [[slot.state, slot.adr, slot.we]
  105
+			for slot in self.slots]
  106
+		comb += multimux(rr.grant, mux_inputs, mux_outputs)
  107
+		comb += [
  108
+			self.stb.eq(state == SLOT_PENDING),
  109
+			rr.ce.eq(self.ack),
  110
+			self.tag.eq(rr.grant)
  111
+		]
  112
+		comb += [slot.process.eq(rr.grant == i & self.ack)
  113
+			for i, slot in enumerate(self.slots)]
  114
+		
  115
+		return Fragment(comb, sync) + rr.get_fragment()
  116
+
  117
+class _Buffer:
  118
+	def __init__(self, source):
  119
+		self.source = source
  120
+		
  121
+		self.stb = Signal()
  122
+		self.ack = Signal()
  123
+		self.tag = Signal(self.source.tag.bv)
  124
+		self.adr = Signal(self.source.adr.bv)
  125
+		self.we = Signal()
  126
+	
  127
+	def get_fragment(self):
  128
+		en = Signal()
  129
+		comb = [
  130
+			en.eq(self.ack | ~self.stb),
  131
+			self.source.ack.eq(en)
  132
+		]
  133
+		sync = [
  134
+			If(en,
  135
+				self.stb.eq(self.source.stb),
  136
+				self.tag.eq(self.source.tag),
  137
+				self.adr.eq(self.source.adr),
  138
+				self.we.eq(self.source.we)
  139
+			)
  140
+		]
  141
+		return Fragment(comb, sync)
  142
+	
3 143
 class BankMachine:
4 144
 	def __init__(self, geom_settings, timing_settings, address_align, bankn, slots):
5  
-		pass
  145
+		self.geom_settings = geom_settings
  146
+		self.timing_settings = timing_settings
  147
+		self.address_align = address_align
  148
+		self.bankn = bankn
  149
+		self.slots = slots
  150
+		
  151
+		self.refresh_req = Signal()
  152
+		self.refresh_gnt = Signal()
  153
+		self.cmd_request = CommandRequestRW(geom_settings.mux_a, geom_settings.bank_a,
  154
+			bits_for(len(slots)-1))
6 155
 
7 156
 	def get_fragment(self):
8  
-		return Fragment()
  157
+		comb = []
  158
+		sync = []
  159
+		
  160
+		# Sub components
  161
+		slicer = _AddressSlicer(self.geom_settings, self.address_align)
  162
+		selector = _Selector(slicer, self.bankn, self.slots)
  163
+		buf = _Buffer(selector)
  164
+		
  165
+		# Row tracking
  166
+		has_openrow = Signal()
  167
+		openrow = Signal(BV(self.geom_settings.row_a))
  168
+		hit = Signal()
  169
+		comb.append(hit.eq(openrow == slicer.row(buf.adr)))
  170
+		track_open = Signal()
  171
+		track_close = Signal()
  172
+		sync += [
  173
+			If(track_open,
  174
+				has_openrow.eq(1),
  175
+				openrow.eq(slicer.row(buf.adr))
  176
+			),
  177
+			If(track_close,
  178
+				has_openrow.eq(0)
  179
+			)
  180
+		]
  181
+		
  182
+		# Address generation
  183
+		s_row_adr = Signal()
  184
+		comb += [
  185
+			self.cmd_request.ba.eq(self.bankn),
  186
+			If(s_row_adr,
  187
+				self.cmd_request.a.eq(slicer.row(buf.adr))
  188
+			).Else(
  189
+				self.cmd_request.a.eq(slicer.col(buf.adr))
  190
+			)
  191
+		]
  192
+		
  193
+		comb.append(self.cmd_request.tag.eq(buf.tag))
  194
+		
  195
+		# Control and command generation FSM
  196
+		fsm = FSM("REGULAR", "PRECHARGE", "ACTIVATE", "REFRESH", delayed_enters=[
  197
+			("TRP", "ACTIVATE", self.timing_settings.tRP-1),
  198
+			("TRCD", "REGULAR", self.timing_settings.tRCD-1)
  199
+		])
  200
+		fsm.act(fsm.REGULAR,
  201
+			If(self.refresh_req,
  202
+				fsm.next_state(fsm.REFRESH)
  203
+			).Elif(buf.stb,
  204
+				If(has_openrow,
  205
+					If(hit,
  206
+						self.cmd_request.stb.eq(1),
  207
+						buf.ack.eq(self.cmd_request.ack),
  208
+						self.cmd_request.is_read.eq(~buf.we),
  209
+						self.cmd_request.is_write.eq(buf.we),
  210
+						self.cmd_request.cas_n.eq(0),
  211
+						self.cmd_request.we_n.eq(~buf.we)
  212
+					).Else(
  213
+						fsm.next_state(fsm.PRECHARGE)
  214
+					)
  215
+				).Else(
  216
+					fsm.next_state(fsm.ACTIVATE)
  217
+				)
  218
+			)
  219
+		)
  220
+		fsm.act(fsm.PRECHARGE,
  221
+			# Notes:
  222
+			# 1. we are presenting the column address, A10 is always low
  223
+			# 2. since we always go to the ACTIVATE state, we do not need
  224
+			# to assert track_close.
  225
+			self.cmd_request.stb.eq(1),
  226
+			If(self.cmd_request.ack, fsm.next_state(fsm.TRP)),
  227
+			self.cmd_request.ras_n.eq(0),
  228
+			self.cmd_request.we_n.eq(0)
  229
+		)
  230
+		fsm.act(fsm.ACTIVATE,
  231
+			s_row_adr.eq(1),
  232
+			track_open.eq(1),
  233
+			self.cmd_request.stb.eq(1),
  234
+			If(self.cmd_request.ack, fsm.next_state(fsm.TRCD)),
  235
+			self.cmd_request.ras_n.eq(0)
  236
+		)
  237
+		fsm.act(fsm.REFRESH,
  238
+			self.refresh_gnt.eq(1),
  239
+			track_close.eq(1),
  240
+			If(~self.refresh_req, fsm.next_state(fsm.REGULAR))
  241
+		)
  242
+		
  243
+		return Fragment(comb, sync) + \
  244
+			selector.get_fragment() + \
  245
+			buf.get_fragment() + \
  246
+			fsm.get_fragment()
10  milkymist/asmicon/multiplexer.py
... ...
@@ -1,16 +1,16 @@
1 1
 from migen.fhdl.structure import *
2 2
 
3 3
 class CommandRequest:
4  
-	def __init__(self, dfi_a, dfi_ba):
5  
-		self.a = Signal(BV(dfi_a))
6  
-		self.ba = Signal(BV(dfi_ba))
  4
+	def __init__(self, a, ba):
  5
+		self.a = Signal(BV(a))
  6
+		self.ba = Signal(BV(ba))
7 7
 		self.cas_n = Signal(reset=1)
8 8
 		self.ras_n = Signal(reset=1)
9 9
 		self.we_n = Signal(reset=1)
10 10
 
11 11
 class CommandRequestRW(CommandRequest):
12  
-	def __init__(self, dfi_a, dfi_ba, tagbits):
13  
-		CommandRequest.__init__(self, dfi_a, dfi_ba)
  12
+	def __init__(self, a, ba, tagbits):
  13
+		CommandRequest.__init__(self, a, ba)
14 14
 		self.stb = Signal()
15 15
 		self.ack = Signal()
16 16
 		self.is_read = Signal()
6  milkymist/asmicon/refresher.py
@@ -5,14 +5,14 @@
5 5
 from milkymist.asmicon.multiplexer import *
6 6
 
7 7
 class Refresher:
8  
-	def __init__(self, dfi_a, dfi_ba, tRP, tREFI, tRFC):
  8
+	def __init__(self, a, ba, tRP, tREFI, tRFC):
9 9
 		self.tRP = tRP
10 10
 		self.tREFI = tREFI
11 11
 		self.tRFC = tRFC
12 12
 		
13 13
 		self.req = Signal()
14 14
 		self.ack = Signal()
15  
-		self.cmd_request = CommandRequest(dfi_a, dfi_ba)
  15
+		self.cmd_request = CommandRequest(a, ba)
16 16
 	
17 17
 	def get_fragment(self):
18 18
 		comb = []
@@ -38,7 +38,7 @@ def get_fragment(self):
38 38
 				self.cmd_request.cas_n.eq(0),
39 39
 				self.cmd_request.ras_n.eq(0)
40 40
 			]),
41  
-			(self.tRP+self.tRFC, [
  41
+			(self.tRP+self.tRFC-1, [
42 42
 				seq_done.eq(1)
43 43
 			])
44 44
 		])
12  top.py
@@ -14,13 +14,12 @@
14 14
 l2_size = 8192 # in bytes
15 15
 
16 16
 clk_period_ns = 1000000000/clk_freq
17  
-def ns(t, margin=False):
  17
+def ns(t, margin=True):
18 18
 	if margin:
19 19
 		t += clk_period_ns/2
20 20
 	return ceil(t/clk_period_ns)
21 21
 
22 22
 sdram_phy = asmicon.PhySettings(
23  
-	dfi_a=13,
24 23
 	dfi_d=64, 
25 24
 	nphases=2,
26 25
 	rdphase=0,
@@ -33,7 +32,8 @@ def ns(t, margin=False):
33 32
 )
34 33
 sdram_timing = asmicon.TimingSettings(
35 34
 	tRP=ns(15),
36  
-	tREFI=ns(7800),
  35
+	tRCD=ns(15),
  36
+	tREFI=ns(7800, False),
37 37
 	tRFC=ns(70)
38 38
 )
39 39
 
@@ -52,15 +52,15 @@ def get():
52 52
 	#
53 53
 	# ASMI
54 54
 	#
55  
-	asmicon0 = asmicon.ASMIcon(sdram_phy, sdram_geom, sdram_timing, 8)
  55
+	asmicon0 = asmicon.ASMIcon(sdram_phy, sdram_geom, sdram_timing, 16)
56 56
 	asmiport_wb = asmicon0.hub.get_port()
57 57
 	asmicon0.finalize()
58 58
 	
59 59
 	#
60 60
 	# DFI
61 61
 	#
62  
-	ddrphy0 = s6ddrphy.S6DDRPHY(sdram_phy.dfi_a, sdram_geom.bank_a, sdram_phy.dfi_d)
63  
-	dfii0 = dfii.DFIInjector(1, sdram_phy.dfi_a, sdram_geom.bank_a, sdram_phy.dfi_d, sdram_phy.nphases)
  62
+	ddrphy0 = s6ddrphy.S6DDRPHY(sdram_geom.mux_a, sdram_geom.bank_a, sdram_phy.dfi_d)
  63
+	dfii0 = dfii.DFIInjector(1, sdram_geom.mux_a, sdram_geom.bank_a, sdram_phy.dfi_d, sdram_phy.nphases)
64 64
 	dficon0 = dfi.Interconnect(dfii0.master, ddrphy0.dfi)
65 65
 	dficon1 = dfi.Interconnect(asmicon0.dfi, dfii0.slave)
66 66
 

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