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Use new ClockDomain API

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commit b2173bba9f4a550de530bef7e8227e744abfd7b1 1 parent 2ae504f
Sébastien Bourdeauducq sbourdeauducq authored
Showing with 9 additions and 10 deletions.
  1. +1 −1  build.py
  2. +8 −9 milkymist/m1crg/__init__.py
2  build.py
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@@ -60,7 +60,7 @@ def main():
"jtag_tap_spartan6.v", "lm32_itlb.v", "lm32_dtlb.v")
plat.add_sources(os.path.join("verilog", "lm32"), "lm32_config.v")
- plat.build_cmdline(soc, clock_domains=soc.crg.get_clock_domains())
+ plat.build_cmdline(soc)
if __name__ == "__main__":
main()
17 milkymist/m1crg/__init__.py
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@@ -3,9 +3,8 @@
from migen.fhdl.structure import *
from migen.fhdl.specials import Instance
from migen.fhdl.module import Module
-from mibuild.crg import CRG
-class M1CRG(Module, CRG):
+class M1CRG(Module):
def __init__(self, infreq, outfreq1x):
self.clk50_pad = Signal()
self.trigger_reset = Signal()
@@ -13,13 +12,13 @@ def __init__(self, infreq, outfreq1x):
self.eth_rx_clk_pad = Signal()
self.eth_tx_clk_pad = Signal()
- self.cd_sys = ClockDomain("sys")
- self.cd_sys2x_270 = ClockDomain("sys2x_270")
- self.cd_sys4x_wr = ClockDomain("sys4x_wr")
- self.cd_sys4x_rd = ClockDomain("sys4x_rd")
- self.cd_eth_rx = ClockDomain("eth_rx")
- self.cd_eth_tx = ClockDomain("eth_tx")
- self.cd_vga = ClockDomain("vga")
+ self.clock_domains.cd_sys = ClockDomain()
+ self.clock_domains.cd_sys2x_270 = ClockDomain()
+ self.clock_domains.cd_sys4x_wr = ClockDomain()
+ self.clock_domains.cd_sys4x_rd = ClockDomain()
+ self.clock_domains.cd_eth_rx = ClockDomain()
+ self.clock_domains.cd_eth_tx = ClockDomain()
+ self.clock_domains.cd_vga = ClockDomain()
ratio = Fraction(outfreq1x)/Fraction(infreq)
in_period = float(Fraction(1000000000)/Fraction(infreq))
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