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Use new ClockDomain API

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commit b2173bba9f4a550de530bef7e8227e744abfd7b1 1 parent 2ae504f
Sébastien Bourdeauducq authored March 15, 2013
2  build.py
@@ -60,7 +60,7 @@ def main():
60 60
 		"jtag_tap_spartan6.v", "lm32_itlb.v", "lm32_dtlb.v")
61 61
 	plat.add_sources(os.path.join("verilog", "lm32"), "lm32_config.v")
62 62
 	
63  
-	plat.build_cmdline(soc, clock_domains=soc.crg.get_clock_domains())
  63
+	plat.build_cmdline(soc)
64 64
 
65 65
 if __name__ == "__main__":
66 66
 	main()
17  milkymist/m1crg/__init__.py
@@ -3,9 +3,8 @@
3 3
 from migen.fhdl.structure import *
4 4
 from migen.fhdl.specials import Instance
5 5
 from migen.fhdl.module import Module
6  
-from mibuild.crg import CRG
7 6
 
8  
-class M1CRG(Module, CRG):
  7
+class M1CRG(Module):
9 8
 	def __init__(self, infreq, outfreq1x):
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 		self.clk50_pad = Signal()
11 10
 		self.trigger_reset = Signal()
@@ -13,13 +12,13 @@ def __init__(self, infreq, outfreq1x):
13 12
 		self.eth_rx_clk_pad = Signal()
14 13
 		self.eth_tx_clk_pad = Signal()
15 14
 		
16  
-		self.cd_sys = ClockDomain("sys")
17  
-		self.cd_sys2x_270 = ClockDomain("sys2x_270")
18  
-		self.cd_sys4x_wr = ClockDomain("sys4x_wr")
19  
-		self.cd_sys4x_rd = ClockDomain("sys4x_rd")
20  
-		self.cd_eth_rx = ClockDomain("eth_rx")
21  
-		self.cd_eth_tx = ClockDomain("eth_tx")
22  
-		self.cd_vga = ClockDomain("vga")
  15
+		self.clock_domains.cd_sys = ClockDomain()
  16
+		self.clock_domains.cd_sys2x_270 = ClockDomain()
  17
+		self.clock_domains.cd_sys4x_wr = ClockDomain()
  18
+		self.clock_domains.cd_sys4x_rd = ClockDomain()
  19
+		self.clock_domains.cd_eth_rx = ClockDomain()
  20
+		self.clock_domains.cd_eth_tx = ClockDomain()
  21
+		self.clock_domains.cd_vga = ClockDomain()
23 22
 		
24 23
 		ratio = Fraction(outfreq1x)/Fraction(infreq)
25 24
 		in_period = float(Fraction(1000000000)/Fraction(infreq))

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