Skip to content
This repository

HTTPS clone URL

Subversion checkout URL

You can clone with HTTPS or Subversion.

Download ZIP
Browse code

s6ddrphy: read path OK in simulation

  • Loading branch information...
commit b3ca952a39d57223575d36a1fa2793ee977c818f 1 parent b4e041e
Sébastien Bourdeauducq authored
45  tb/s6ddrphy/gtkwave.sav
... ...
@@ -0,0 +1,45 @@
  1
+[timestart] 0
  2
+[size] 1741 771
  3
+[pos] -1 -1
  4
+*-14.000000 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
  5
+[treeopen] tb_s6ddrphy.
  6
+[treeopen] tb_s6ddrphy.dut.
  7
+[treeopen] tb_s6ddrphy.dut.gen_dq[0].
  8
+@28
  9
+tb_s6ddrphy.dut.sys_clk
  10
+tb_s6ddrphy.dut.clk2x_270
  11
+tb_s6ddrphy.dut.clk4x_wr
  12
+tb_s6ddrphy.dut.clk4x_wr_strb
  13
+@22
  14
+tb_s6ddrphy.dut.dfi_address_p0[12:0]
  15
+tb_s6ddrphy.dut.dfi_address_p1[12:0]
  16
+@200
  17
+-
  18
+@22
  19
+tb_s6ddrphy.dut.sd_a[12:0]
  20
+@28
  21
+tb_s6ddrphy.dut.sd_clk_out_p
  22
+@22
  23
+tb_s6ddrphy.dut.sd_dm[3:0]
  24
+tb_s6ddrphy.dut.sd_dq[31:0]
  25
+tb_s6ddrphy.dut.sd_dqs[3:0]
  26
+@200
  27
+-
  28
+@28
  29
+tb_s6ddrphy.dut.dfi_wrdata_en_p1
  30
+@22
  31
+tb_s6ddrphy.dut.dfi_wrdata_mask_p0[7:0]
  32
+tb_s6ddrphy.dut.dfi_wrdata_mask_p1[7:0]
  33
+tb_s6ddrphy.dut.dfi_wrdata_p0[63:0]
  34
+tb_s6ddrphy.dut.dfi_wrdata_p1[63:0]
  35
+@200
  36
+-
  37
+@29
  38
+tb_s6ddrphy.dut.dfi_rddata_en_p0
  39
+@22
  40
+tb_s6ddrphy.dut.dfi_rddata_w0[63:0]
  41
+tb_s6ddrphy.dut.dfi_rddata_w1[63:0]
  42
+@28
  43
+tb_s6ddrphy.dut.dfi_rddata_valid_w0
  44
+[pattern_trace] 1
  45
+[pattern_trace] 0
72  tb/s6ddrphy/tb_s6ddrphy.v
@@ -58,6 +58,13 @@ reg dfi_wrdata_en_p1 = 0;
58 58
 reg [7:0] dfi_wrdata_mask_p1 = 0;
59 59
 reg [63:0] dfi_wrdata_p1 = 0;
60 60
 
  61
+reg dfi_rddata_en_p0 = 0;
  62
+reg dfi_rddata_en_p1 = 0;
  63
+
  64
+wire [31:0] sd_dq;
  65
+reg [31:0] dq_tb = 32'hzzzzzzzz;
  66
+assign sd_dq = dq_tb;
  67
+
61 68
 s6ddrphy #(
62 69
 	.NUM_AD(13),
63 70
 	.NUM_BA(2),
@@ -83,37 +90,76 @@ s6ddrphy #(
83 90
 	.dfi_wrdata_en_p1(dfi_wrdata_en_p1),
84 91
 	.dfi_wrdata_mask_p1(dfi_wrdata_mask_p1),
85 92
 	.dfi_wrdata_p1(dfi_wrdata_p1),
86  
-	.sd_dq(),
  93
+	.sd_dq(sd_dq),
87 94
 	.sd_dm(),
88  
-	.sd_dqs()
  95
+	.sd_dqs(),
  96
+	
  97
+	.dfi_rddata_en_p0(dfi_rddata_en_p0),
  98
+	.dfi_rddata_en_p1(dfi_rddata_en_p1),
  99
+	.dfi_rddata_w0(),
  100
+	.dfi_rddata_w1(),
  101
+	.dfi_rddata_valid_w0(),
  102
+	.dfi_rddata_valid_w1()
89 103
 );
90 104
 
  105
+`define TEST_SIMPLE_CMD
  106
+`define TEST_WRITE
  107
+`define TEST_READ
  108
+
91 109
 initial begin
92 110
 	$dumpfile("s6ddrphy.vcd");
93 111
 	$dumpvars(3, dut);
  112
+
  113
+`ifdef TEST_SIMPLE_CMD
94 114
 	#13;
95  
-	
96  
-	/*dfi_address_p0 <= 13'h1aba;
  115
+	dfi_address_p0 <= 13'h1aba;
97 116
 	dfi_address_p1 <= 13'h1234;
98 117
 	#12;
99 118
 	dfi_address_p0 <= 0;
100 119
 	dfi_address_p1 <= 0;
101  
-	#60;*/
102  
-	
103  
-	dfi_address_p0 <= 13'h0dea;
  120
+	#59;
  121
+`endif
  122
+
  123
+`ifdef TEST_WRITE
  124
+	#13;
104 125
 	dfi_address_p1 <= 13'h0dbe;
  126
+	#12;
  127
+	dfi_address_p1 <= 0;
  128
+	dfi_wrdata_en_p1 <= 1;
  129
+	dfi_wrdata_mask_p0 <= 8'h12;
  130
+	dfi_wrdata_mask_p1 <= 8'h34;
105 131
 	dfi_wrdata_p0 <= 64'hcafebabeabadface;
106 132
 	dfi_wrdata_p1 <= 64'h0123456789abcdef;
107  
-	dfi_wrdata_en_p0 <= 1'b1;
108  
-	dfi_wrdata_en_p1 <= 1'b1;
109 133
 	#12;
110  
-	dfi_address_p0 <= 0;
111  
-	dfi_address_p1 <= 0;
  134
+	dfi_wrdata_en_p1 <= 0;
  135
+	dfi_wrdata_mask_p0 <= 0;
  136
+	dfi_wrdata_mask_p1 <= 0;
112 137
 	dfi_wrdata_p0 <= 64'd0;
113 138
 	dfi_wrdata_p1 <= 64'd0;
114  
-	dfi_wrdata_en_p0 <= 1'b0;
115  
-	dfi_wrdata_en_p1 <= 1'b0;
  139
+	#59;
  140
+`endif
  141
+
  142
+`ifdef TEST_READ
  143
+	#13;
  144
+	dfi_address_p0 <= 13'h1234;
  145
+	#12;
  146
+	dfi_address_p0 <= 0;
  147
+	dfi_rddata_en_p0 <= 1;
  148
+	#12;
  149
+	dfi_rddata_en_p0 <= 0;
  150
+	#15.5;
  151
+	dq_tb <= 32'h12345678;
  152
+	#3;
  153
+	dq_tb <= 32'hdeadbeef;
  154
+	#3;
  155
+	dq_tb <= 32'hcafebabe;
  156
+	#3;
  157
+	dq_tb <= 32'habadface;
  158
+	#3;
  159
+	dq_tb <= 32'hzzzzzzzz;
116 160
 	#60;
  161
+`endif
  162
+	
117 163
 	$finish;
118 164
 end
119 165
 
44  verilog/s6ddrphy/s6ddrphy.v
... ...
@@ -1,6 +1,21 @@
1 1
 /*
2  
- * 1:2 DDR PHY for Spartan-6
  2
+ * 1:2 frequency-ratio DDR PHY for Spartan-6
3 3
  *
  4
+ ************* DATAPATH SIGNALS ***********
  5
+ * Assert dfi_wrdata_en and present the data 
  6
+ * on dfi_wrdata_mask/dfi_wrdata one cycle after
  7
+ * a write command. 
  8
+ *
  9
+ * Assert dfi_rddata_en one cycle after a read
  10
+ * command. The data will come back on dfi_rddata
  11
+ * 3 cycles later, along with the assertion of
  12
+ * dfi_rddata_valid.
  13
+ *
  14
+ * This PHY only supports CAS Latency 3.
  15
+ * Read commands must be sent on phase 0.
  16
+ * Write commands must be sent on phase 1.
  17
+ *
  18
+ ************* DETAILED TIMING ************
4 19
  * Command path:
5 20
  *   posedge sys_clk             + 1
6 21
  *   posedge clk2x_270           + 0.375
@@ -17,8 +32,6 @@
17 32
  *   posedge clk2x_270           + 0.375
18 33
  *   negedge clk2x_270 [oddr]    + 0.125
19 34
  * DQS OE latency                1.5 cycles
20  
- *
21  
- * Data read path:
22 35
  */
23 36
 module s6ddrphy #(
24 37
 	parameter NUM_AD = 0,
@@ -309,7 +322,7 @@ generate
309 322
 			.CLK1(1'b0),
310 323
 			.IOCE(clk4x_rd_strb),
311 324
 			.RST(1'b0),
312  
-			.CLKDIV(clk),
  325
+			.CLKDIV(sys_clk),
313 326
 			.SHIFTIN(),
314 327
 			.BITSLIP(1'b0),
315 328
 			.FABRICOUT(),
@@ -377,25 +390,22 @@ endgenerate
377 390
  * DQ/DQS/DM control
378 391
  */
379 392
 
380  
-reg r_dfi_wrdata_en_p0;
381 393
 reg r_dfi_wrdata_en_p1;
382  
-
383  
-always @(posedge sys_clk) begin
384  
-	r_dfi_wrdata_en_p0 <= dfi_wrdata_en_p0;
  394
+always @(posedge sys_clk)
385 395
 	r_dfi_wrdata_en_p1 <= dfi_wrdata_en_p1;
386  
-end
387 396
 
388  
-reg r2_dfi_wrdata_en_p0;
389 397
 reg r2_dfi_wrdata_en_p1;
390  
-
391  
-always @(posedge clk2x_270) begin
392  
-	r2_dfi_wrdata_en_p0 <= r_dfi_wrdata_en_p0;
  398
+always @(posedge clk2x_270)
393 399
 	r2_dfi_wrdata_en_p1 <= r_dfi_wrdata_en_p1;
394  
-end
395 400
 
396  
-assign drive_dqs = r2_dfi_wrdata_en_p0 | r2_dfi_wrdata_en_p1;
397  
-assign drive_dq = dfi_wrdata_en_p0 | dfi_wrdata_en_p1;
  401
+assign drive_dqs = r2_dfi_wrdata_en_p1;
  402
+assign drive_dq = dfi_wrdata_en_p1;
398 403
 
399  
-// TODO: dfi_rddata_valid_w0/1?
  404
+wire rddata_valid;
  405
+reg [3:0] rddata_sr;
  406
+assign dfi_rddata_valid_w0 = rddata_sr[0];
  407
+assign dfi_rddata_valid_w1 = rddata_sr[0];
  408
+always @(posedge sys_clk)
  409
+	rddata_sr <= {dfi_rddata_en_p0, rddata_sr[3:1]};
400 410
 
401 411
 endmodule

0 notes on commit b3ca952

Please sign in to comment.
Something went wrong with that request. Please try again.