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s6ddrphy: write path OK in simulation

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commit b4e041ecf162fbeee3f894d188037674d20b3205 1 parent ce51653
Sébastien Bourdeauducq authored February 20, 2012
2  milkymist/m1crg/__init__.py
@@ -14,7 +14,7 @@ def __init__(self, infreq, outfreq1x):
14 14
 			"ac97_rst_n",
15 15
 			"videoin_rst_n",
16 16
 			"flash_rst_n",
17  
-			"clk2x_90",
  17
+			"clk2x_270",
18 18
 			"clk4x_wr",
19 19
 			"clk4x_wr_strb",
20 20
 			"clk4x_rd",
2  milkymist/s6ddrphy/__init__.py
@@ -8,7 +8,7 @@ def __init__(self, a, ba, d):
8 8
 		inouts = []
9 9
 		
10 10
 		for name in [
11  
-			"clk2x_90",
  11
+			"clk2x_270",
12 12
 			"clk4x_wr",
13 13
 			"clk4x_wr_strb",
14 14
 			"clk4x_rd",
23  tb/s6ddrphy/Makefile
... ...
@@ -0,0 +1,23 @@
  1
+SOURCES=tb_s6ddrphy.v ../../verilog/s6ddrphy/s6ddrphy.v \
  2
+	$(XILINX)/verilog/src/unisims/ODDR2.v \
  3
+	$(XILINX)/verilog/src/unisims/OSERDES2.v \
  4
+	$(XILINX)/verilog/src/unisims/ISERDES2.v \
  5
+	$(XILINX)/verilog/src/unisims/IOBUF.v \
  6
+	$(XILINX)/verilog/src/unisims/OBUFT.v \
  7
+	$(XILINX)/verilog/src/unisims/BUFPLL.v
  8
+
  9
+all: tb_s6ddrphy
  10
+
  11
+isim: tb_s6ddrphy
  12
+	./tb_s6ddrphy
  13
+
  14
+cversim: $(SOURCES)
  15
+	cver $(SOURCES)
  16
+
  17
+clean:
  18
+	rm -f tb_s6ddrphy verilog.log s6ddrphy.vcd
  19
+
  20
+tb_s6ddrphy: $(SOURCES)
  21
+	iverilog -o tb_s6ddrphy $(SOURCES)
  22
+
  23
+.PHONY: clean sim cversim
125  tb/s6ddrphy/tb_s6ddrphy.v
... ...
@@ -0,0 +1,125 @@
  1
+`timescale 1ns / 1ps
  2
+
  3
+module tb_s6ddrphy();
  4
+
  5
+reg sys_clk = 1'b0;
  6
+reg clk2x_270 = 1'b0;
  7
+reg clk4x_wr = 1'b0;
  8
+wire clk4x_wr_strb;
  9
+wire clk4x_rd = clk4x_wr;
  10
+wire clk4x_rd_strb = clk4x_wr_strb;
  11
+
  12
+initial begin
  13
+	while(1) begin
  14
+		sys_clk <= 1'b1;
  15
+		#6;
  16
+		sys_clk <= 1'b0;
  17
+		#6;
  18
+	end
  19
+end
  20
+
  21
+initial begin
  22
+	#4.5;
  23
+	while(1) begin
  24
+		clk2x_270 <= 1'b1;
  25
+		#3;
  26
+		clk2x_270 <= 1'b0;
  27
+		#3;
  28
+	end
  29
+end
  30
+
  31
+initial begin
  32
+	while(1) begin
  33
+		clk4x_wr <= 1'b1;
  34
+		#1.5;
  35
+		clk4x_wr <= 1'b0;
  36
+		#1.5;
  37
+	end
  38
+end
  39
+
  40
+BUFPLL #(
  41
+	.DIVIDE(4)
  42
+) bufpll (
  43
+	.PLLIN(clk4x_wr),
  44
+	.GCLK(sys_clk),
  45
+	.LOCKED(1'b1),
  46
+	.IOCLK(),
  47
+	.LOCK(),
  48
+	.SERDESSTROBE(clk4x_wr_strb)
  49
+);
  50
+
  51
+reg [12:0] dfi_address_p0 = 0;
  52
+reg [12:0] dfi_address_p1 = 0;
  53
+
  54
+reg dfi_wrdata_en_p0 = 0;
  55
+reg [7:0] dfi_wrdata_mask_p0 = 0;
  56
+reg [63:0] dfi_wrdata_p0 = 0;
  57
+reg dfi_wrdata_en_p1 = 0;
  58
+reg [7:0] dfi_wrdata_mask_p1 = 0;
  59
+reg [63:0] dfi_wrdata_p1 = 0;
  60
+
  61
+s6ddrphy #(
  62
+	.NUM_AD(13),
  63
+	.NUM_BA(2),
  64
+	.NUM_D(64)
  65
+) dut (
  66
+	.sys_clk(sys_clk),
  67
+	.clk2x_270(clk2x_270),
  68
+	.clk4x_wr(clk4x_wr),
  69
+	.clk4x_wr_strb(clk4x_wr_strb),
  70
+	.clk4x_rd(clk4x_rd),
  71
+	.clk4x_rd_strb(clk4x_rd_strb),
  72
+	
  73
+	.sd_clk_out_p(),
  74
+	.sd_clk_out_n(),
  75
+	
  76
+	.dfi_address_p0(dfi_address_p0),
  77
+	.dfi_address_p1(dfi_address_p1),
  78
+	.sd_a(),
  79
+	
  80
+	.dfi_wrdata_en_p0(dfi_wrdata_en_p0),
  81
+	.dfi_wrdata_mask_p0(dfi_wrdata_mask_p0),
  82
+	.dfi_wrdata_p0(dfi_wrdata_p0),
  83
+	.dfi_wrdata_en_p1(dfi_wrdata_en_p1),
  84
+	.dfi_wrdata_mask_p1(dfi_wrdata_mask_p1),
  85
+	.dfi_wrdata_p1(dfi_wrdata_p1),
  86
+	.sd_dq(),
  87
+	.sd_dm(),
  88
+	.sd_dqs()
  89
+);
  90
+
  91
+initial begin
  92
+	$dumpfile("s6ddrphy.vcd");
  93
+	$dumpvars(3, dut);
  94
+	#13;
  95
+	
  96
+	/*dfi_address_p0 <= 13'h1aba;
  97
+	dfi_address_p1 <= 13'h1234;
  98
+	#12;
  99
+	dfi_address_p0 <= 0;
  100
+	dfi_address_p1 <= 0;
  101
+	#60;*/
  102
+	
  103
+	dfi_address_p0 <= 13'h0dea;
  104
+	dfi_address_p1 <= 13'h0dbe;
  105
+	dfi_wrdata_p0 <= 64'hcafebabeabadface;
  106
+	dfi_wrdata_p1 <= 64'h0123456789abcdef;
  107
+	dfi_wrdata_en_p0 <= 1'b1;
  108
+	dfi_wrdata_en_p1 <= 1'b1;
  109
+	#12;
  110
+	dfi_address_p0 <= 0;
  111
+	dfi_address_p1 <= 0;
  112
+	dfi_wrdata_p0 <= 64'd0;
  113
+	dfi_wrdata_p1 <= 64'd0;
  114
+	dfi_wrdata_en_p0 <= 1'b0;
  115
+	dfi_wrdata_en_p1 <= 1'b0;
  116
+	#60;
  117
+	$finish;
  118
+end
  119
+
  120
+endmodule
  121
+
  122
+module glbl();
  123
+wire GSR = 1'b0;
  124
+wire GTS = 1'b0;
  125
+endmodule
2  top.py
@@ -18,7 +18,7 @@
18 18
 
19 19
 def ddrphy_clocking(crg, phy):
20 20
 	names = [
21  
-		"clk2x_90",
  21
+		"clk2x_270",
22 22
 		"clk4x_wr",
23 23
 		"clk4x_wr_strb",
24 24
 		"clk4x_rd",
6  verilog/m1crg/m1crg.v
@@ -33,7 +33,7 @@ module m1crg #(
33 33
 	output flash_rst_n,
34 34
 	
35 35
 	/* DDR PHY clocks */
36  
-	output clk2x_90,
  36
+	output clk2x_270,
37 37
 	output clk4x_wr,
38 38
 	output clk4x_wr_strb,
39 39
 	output clk4x_rd,
@@ -122,7 +122,7 @@ PLL_ADV #(
122 122
 	.CLKOUT1_PHASE(0),
123 123
 	.CLKOUT2_DIVIDE(2*f_div),
124 124
 	.CLKOUT2_DUTY_CYCLE(0.5),
125  
-	.CLKOUT2_PHASE(90.0),
  125
+	.CLKOUT2_PHASE(270.0),
126 126
 	.CLKOUT3_DIVIDE(4*f_div),
127 127
 	.CLKOUT3_DUTY_CYCLE(0.5),
128 128
 	.CLKOUT3_PHASE(0.0),
@@ -192,7 +192,7 @@ BUFPLL #(
192 192
 
193 193
 BUFG bufg_x2_2(
194 194
 	.I(pllout2),
195  
-	.O(clk2x_90)
  195
+	.O(clk2x_270)
196 196
 );
197 197
 
198 198
 BUFG bufg_x1(
111  verilog/s6ddrphy/s6ddrphy.v
@@ -3,9 +3,9 @@
3 3
  *
4 4
  * Command path:
5 5
  *   posedge sys_clk             + 1
6  
- *   negedge clk2x_90            + 0.375
7  
- *   negedge clk2x_90            + 0.5
8  
- * Command latency:              1.875 cycles
  6
+ *   posedge clk2x_270           + 0.375
  7
+ *   negedge clk2x_270           + 0.125
  8
+ * Command latency:              1.5 cycles
9 9
  *
10 10
  * Data write path (phase 0, word 0):
11 11
  *   posedge sys_clk [oserdes]   + 1
@@ -14,9 +14,9 @@
14 14
  *
15 15
  * DQS OE path:
16 16
  *   posedge sys_clk             + 1
17  
- *   negedge clk2x_90            + 0.375
18  
- *   negedge clk2x_90 [oddr]     + 0.5
19  
- * DQS OE latency                1.875 cycles
  17
+ *   posedge clk2x_270           + 0.375
  18
+ *   negedge clk2x_270 [oddr]    + 0.125
  19
+ * DQS OE latency                1.5 cycles
20 20
  *
21 21
  * Data read path:
22 22
  */
@@ -27,7 +27,7 @@ module s6ddrphy #(
27 27
 ) (
28 28
 	/* Clocks */
29 29
 	input sys_clk,
30  
-	input clk2x_90,
  30
+	input clk2x_270,
31 31
 	input clk4x_wr,
32 32
 	input clk4x_wr_strb,
33 33
 	input clk4x_rd,
@@ -87,8 +87,8 @@ ODDR2 #(
87 87
 	.SRTYPE("SYNC")
88 88
 ) sd_clk_forward_p (
89 89
 	.Q(sd_clk_out_p),
90  
-	.C0(clk2x_90),
91  
-	.C1(~clk2x_90),
  90
+	.C0(clk2x_270),
  91
+	.C1(~clk2x_270),
92 92
 	.CE(1'b1),
93 93
 	.D0(1'b1),
94 94
 	.D1(1'b0),
@@ -101,8 +101,8 @@ ODDR2 #(
101 101
 	.SRTYPE("SYNC")
102 102
 ) sd_clk_forward_n (
103 103
 	.Q(sd_clk_out_n),
104  
-	.C0(clk2x_90),
105  
-	.C1(~clk2x_90),
  104
+	.C0(clk2x_270),
  105
+	.C1(~clk2x_270),
106 106
 	.CE(1'b1),
107 107
 	.D0(1'b0),
108 108
 	.D1(1'b1),
@@ -115,7 +115,7 @@ ODDR2 #(
115 115
  */
116 116
 
117 117
 reg phase_sel;
118  
-always @(negedge clk2x_90)
  118
+always @(negedge clk2x_270)
119 119
 	phase_sel <= sys_clk;
120 120
 
121 121
 reg [NUM_AD-1:0] r_dfi_address_p0;
@@ -166,7 +166,7 @@ reg r2_dfi_ras_n_p1;
166 166
 reg r2_dfi_cas_n_p1;
167 167
 reg r2_dfi_we_n_p1;
168 168
 	
169  
-always @(negedge clk2x_90) begin
  169
+always @(posedge clk2x_270) begin
170 170
 	r2_dfi_address_p0 <= r_dfi_address_p0;
171 171
 	r2_dfi_bank_p0 <= r_dfi_bank_p0;
172 172
 	r2_dfi_cs_n_p0 <= r_dfi_cs_n_p0;
@@ -184,16 +184,8 @@ always @(negedge clk2x_90) begin
184 184
 	r2_dfi_we_n_p1 <= r_dfi_we_n_p1;
185 185
 end
186 186
 
187  
-always @(negedge clk2x_90) begin
  187
+always @(negedge clk2x_270) begin
188 188
 	if(phase_sel) begin
189  
-		sd_a <= r2_dfi_address_p1;
190  
-		sd_ba <= r2_dfi_bank_p1;
191  
-		sd_cs_n <= r2_dfi_cs_n_p1;
192  
-		sd_cke <= r2_dfi_cke_p1;
193  
-		sd_ras_n <= r2_dfi_ras_n_p1;
194  
-		sd_cas_n <= r2_dfi_cas_n_p1;
195  
-		sd_we_n <= r2_dfi_we_n_p1;
196  
-	end else begin
197 189
 		sd_a <= r2_dfi_address_p0;
198 190
 		sd_ba <= r2_dfi_bank_p0;
199 191
 		sd_cs_n <= r2_dfi_cs_n_p0;
@@ -201,6 +193,14 @@ always @(negedge clk2x_90) begin
201 193
 		sd_ras_n <= r2_dfi_ras_n_p0;
202 194
 		sd_cas_n <= r2_dfi_cas_n_p0;
203 195
 		sd_we_n <= r2_dfi_we_n_p0;
  196
+	end else begin
  197
+		sd_a <= r2_dfi_address_p1;
  198
+		sd_ba <= r2_dfi_bank_p1;
  199
+		sd_cs_n <= r2_dfi_cs_n_p1;
  200
+		sd_cke <= r2_dfi_cke_p1;
  201
+		sd_ras_n <= r2_dfi_ras_n_p1;
  202
+		sd_cas_n <= r2_dfi_cas_n_p1;
  203
+		sd_we_n <= r2_dfi_we_n_p1;
204 204
 	end
205 205
 end
206 206
 
@@ -210,10 +210,10 @@ end
210 210
 
211 211
 genvar i;
212 212
 
213  
-wire drive_dqs_p0;
214  
-wire drive_dqs_p1;
  213
+wire drive_dqs;
215 214
 wire [NUM_D/16-1:0] dqs_o;
216 215
 wire [NUM_D/16-1:0] dqs_t;
  216
+reg postamble;
217 217
 generate
218 218
 	for(i=0;i<NUM_D/16;i=i+1)
219 219
 	begin: gen_dqs
@@ -223,8 +223,8 @@ generate
223 223
 			.SRTYPE("ASYNC")
224 224
 		) dqs_o_oddr (
225 225
 			.Q(dqs_o[i]),
226  
-			.C0(clk2x_90),
227  
-			.C1(~clk2x_90),
  226
+			.C0(clk2x_270),
  227
+			.C1(~clk2x_270),
228 228
 			.CE(1'b1),
229 229
 			.D0(1'b0),
230 230
 			.D1(1'b1),
@@ -237,11 +237,11 @@ generate
237 237
 			.SRTYPE("ASYNC")
238 238
 		) dqs_t_oddr (
239 239
 			.Q(dqs_t[i]),
240  
-			.C0(clk2x_90),
241  
-			.C1(~clk2x_90),
  240
+			.C0(clk2x_270),
  241
+			.C1(~clk2x_270),
242 242
 			.CE(1'b1),
243  
-			.D0(~drive_dqs_p0),
244  
-			.D1(~drive_dqs_p1),
  243
+			.D0(~(drive_dqs | postamble)),
  244
+			.D1(~drive_dqs),
245 245
 			.R(1'b0),
246 246
 			.S(1'b0)
247 247
 		);
@@ -252,9 +252,10 @@ generate
252 252
 		);
253 253
 	end
254 254
 endgenerate
  255
+always @(posedge clk2x_270)
  256
+	postamble <= drive_dqs;
255 257
 
256  
-wire drive_dq_p0;
257  
-wire drive_dq_p1;
  258
+wire drive_dq;
258 259
 wire [NUM_D/2-1:0] dq_i;
259 260
 wire [NUM_D/2-1:0] dq_o;
260 261
 wire [NUM_D/2-1:0] dq_t;
@@ -273,17 +274,17 @@ generate
273 274
 			.CLK0(clk4x_wr),
274 275
 			.CLK1(1'b0),
275 276
 			.IOCE(clk4x_wr_strb),
276  
-			.RST(),
  277
+			.RST(1'b0),
277 278
 			.CLKDIV(sys_clk),
278  
-			.D1(dfi_wrdata_p0[2*i]),
279  
-			.D2(dfi_wrdata_p0[2*i+1]),
280  
-			.D3(dfi_wrdata_p1[2*i]),
281  
-			.D4(dfi_wrdata_p1[2*i+1]),
  279
+			.D1(dfi_wrdata_p0[i+NUM_D/2]),
  280
+			.D2(dfi_wrdata_p0[i]),
  281
+			.D3(dfi_wrdata_p1[i+NUM_D/2]),
  282
+			.D4(dfi_wrdata_p1[i]),
282 283
 			.TQ(dq_t[i]),
283  
-			.T1(~drive_dq_p0),
284  
-			.T2(~drive_dq_p0),
285  
-			.T3(~drive_dq_p1),
286  
-			.T4(~drive_dq_p1),
  284
+			.T1(~drive_dq),
  285
+			.T2(~drive_dq),
  286
+			.T3(~drive_dq),
  287
+			.T4(~drive_dq),
287 288
 			.TRAIN(1'b0),
288 289
 			.TCE(1'b1),
289 290
 			.SHIFTIN1(1'b0),
@@ -307,15 +308,15 @@ generate
307 308
 			.CLK0(clk4x_rd),
308 309
 			.CLK1(1'b0),
309 310
 			.IOCE(clk4x_rd_strb),
310  
-			.RST(),
  311
+			.RST(1'b0),
311 312
 			.CLKDIV(clk),
312 313
 			.SHIFTIN(),
313 314
 			.BITSLIP(1'b0),
314 315
 			.FABRICOUT(),
315  
-			.Q1(dfi_rddata_w0[2*i]),
316  
-			.Q2(dfi_rddata_w0[2*i+1]),
317  
-			.Q3(dfi_rddata_w1[2*i]),
318  
-			.Q4(dfi_rddata_w1[2*i+1]),
  316
+			.Q1(dfi_rddata_w0[i+NUM_D/2]),
  317
+			.Q2(dfi_rddata_w0[i]),
  318
+			.Q3(dfi_rddata_w1[i+NUM_D/2]),
  319
+			.Q4(dfi_rddata_w1[i]),
319 320
 			.DFB(),
320 321
 			.CFB0(),
321 322
 			.CFB1(),
@@ -347,12 +348,12 @@ generate
347 348
 			.CLK0(clk4x_wr),
348 349
 			.CLK1(1'b0),
349 350
 			.IOCE(clk4x_wr_strb),
350  
-			.RST(),
  351
+			.RST(1'b0),
351 352
 			.CLKDIV(sys_clk),
352  
-			.D1(dfi_wrdata_mask_p0[2*i]),
353  
-			.D2(dfi_wrdata_mask_p0[2*i+1]),
354  
-			.D3(dfi_wrdata_mask_p1[2*i]),
355  
-			.D4(dfi_wrdata_mask_p1[2*i+1]),
  353
+			.D1(dfi_wrdata_mask_p0[i+NUM_D/16]),
  354
+			.D2(dfi_wrdata_mask_p0[i]),
  355
+			.D3(dfi_wrdata_mask_p1[i+NUM_D/16]),
  356
+			.D4(dfi_wrdata_mask_p1[i]),
356 357
 			.TQ(),
357 358
 			.T1(),
358 359
 			.T2(),
@@ -387,15 +388,13 @@ end
387 388
 reg r2_dfi_wrdata_en_p0;
388 389
 reg r2_dfi_wrdata_en_p1;
389 390
 
390  
-always @(negedge clk2x_90) begin
  391
+always @(posedge clk2x_270) begin
391 392
 	r2_dfi_wrdata_en_p0 <= r_dfi_wrdata_en_p0;
392 393
 	r2_dfi_wrdata_en_p1 <= r_dfi_wrdata_en_p1;
393 394
 end
394 395
 
395  
-assign drive_dqs_p0 = r2_dfi_wrdata_en_p0;
396  
-assign drive_dqs_p1 = r2_dfi_wrdata_en_p1;
397  
-assign drive_dq_p0 = dfi_wrdata_en_p0;
398  
-assign drive_dq_p1 = dfi_wrdata_en_p1;
  396
+assign drive_dqs = r2_dfi_wrdata_en_p0 | r2_dfi_wrdata_en_p1;
  397
+assign drive_dq = dfi_wrdata_en_p0 | dfi_wrdata_en_p1;
399 398
 
400 399
 // TODO: dfi_rddata_valid_w0/1?
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