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Convert -> convert

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commit b60abfaa4a47dc60189ecabea5f891b6597f7179 1 parent 3b640c4
Sébastien Bourdeauducq authored January 05, 2012
2  build.py
@@ -31,7 +31,7 @@ def str2file(filename, contents):
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 str2file("soc.v", src_verilog)
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 str2file("soc.ucf", src_ucf)
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 verilog_sources.append("build/soc.v")
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-
  34
+#raise SystemExit
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 # xst
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 xst_prj = ""
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 for s in verilog_sources:
2  milkymist/uart/__init__.py
@@ -14,7 +14,7 @@ def __init__(self, address, clk_freq, baud=115200):
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 		self.tx = Signal(reset=1)
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 		self.rx = Signal()
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-		self.divisor = int(clk_freq/baud/16); # TODO
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+		self.divisor = int(clk_freq/baud/16) # TODO
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 	def get_fragment(self):
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 		enable16 = Signal()
2  tb/norflash/norflash_conv.py
@@ -5,6 +5,6 @@
5 5
 
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 norflash0 = norflash.Inst(25, 12)
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 frag = norflash0.get_fragment()
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-v = verilog.Convert(frag, name="norflash",
  8
+v = verilog.convert(frag, name="norflash",
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 	ios={norflash0.bus.cyc_i, norflash0.bus.stb_i, norflash0.bus.we_i, norflash0.bus.adr_i, norflash0.bus.sel_i, norflash0.bus.dat_i, norflash0.bus.dat_o, norflash0.bus.ack_o})
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 print(v)
2  top.py
@@ -25,7 +25,7 @@ def get():
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 	frag = autofragment.from_local()
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 	vns = convtools.Namespace()
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-	src_verilog = verilog.Convert(frag,
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+	src_verilog = verilog.convert(frag,
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 		{clkfx_sys.clkin, reset0.trigger_reset},
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 		name="soc",
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 		clk_signal=clkfx_sys.clkout,

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