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Convert -> convert

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commit b60abfaa4a47dc60189ecabea5f891b6597f7179 1 parent 3b640c4
@sbourdeauducq sbourdeauducq authored
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2  build.py
@@ -31,7 +31,7 @@ def str2file(filename, contents):
str2file("soc.v", src_verilog)
str2file("soc.ucf", src_ucf)
verilog_sources.append("build/soc.v")
-
+#raise SystemExit
# xst
xst_prj = ""
for s in verilog_sources:
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2  milkymist/uart/__init__.py
@@ -14,7 +14,7 @@ def __init__(self, address, clk_freq, baud=115200):
self.tx = Signal(reset=1)
self.rx = Signal()
- self.divisor = int(clk_freq/baud/16); # TODO
+ self.divisor = int(clk_freq/baud/16) # TODO
def get_fragment(self):
enable16 = Signal()
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2  tb/norflash/norflash_conv.py
@@ -5,6 +5,6 @@
norflash0 = norflash.Inst(25, 12)
frag = norflash0.get_fragment()
-v = verilog.Convert(frag, name="norflash",
+v = verilog.convert(frag, name="norflash",
ios={norflash0.bus.cyc_i, norflash0.bus.stb_i, norflash0.bus.we_i, norflash0.bus.adr_i, norflash0.bus.sel_i, norflash0.bus.dat_i, norflash0.bus.dat_o, norflash0.bus.ack_o})
print(v)
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2  top.py
@@ -25,7 +25,7 @@ def get():
frag = autofragment.from_local()
vns = convtools.Namespace()
- src_verilog = verilog.Convert(frag,
+ src_verilog = verilog.convert(frag,
{clkfx_sys.clkin, reset0.trigger_reset},
name="soc",
clk_signal=clkfx_sys.clkout,
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