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build: support optional MMU

1 parent 43343b1 commit b854f1ad32338e8eb5336bc62b2817117857096f @sbourdeauducq sbourdeauducq committed
Showing with 1 addition and 1 deletion.
  1. +1 −1
@@ -55,7 +55,7 @@ def main():
"lm32_shifter.v", "lm32_multiplier.v", "lm32_mc_arithmetic.v",
"lm32_interrupt.v", "lm32_ram.v", "lm32_dp_ram.v", "lm32_icache.v",
"lm32_dcache.v", "lm32_top.v", "lm32_debug.v", "lm32_jtag.v", "jtag_cores.v",
- "jtag_tap_spartan6.v")
+ "jtag_tap_spartan6.v", "lm32_itlb.v", "lm32_dtlb.v")
plat.add_sources(os.path.join("verilog", "lm32"), "lm32_config.v")
plat.build_cmdline(soc.get_fragment(), clock_domains=soc.crg.get_clock_domains())

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