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build: support optional MMU

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commit b854f1ad32338e8eb5336bc62b2817117857096f 1 parent 43343b1
Sébastien Bourdeauducq authored February 24, 2013

Showing 1 changed file with 1 addition and 1 deletion. Show diff stats Hide diff stats

  1. 2  build.py
2  build.py
@@ -55,7 +55,7 @@ def main():
55 55
 		"lm32_shifter.v", "lm32_multiplier.v", "lm32_mc_arithmetic.v",
56 56
 		"lm32_interrupt.v", "lm32_ram.v", "lm32_dp_ram.v", "lm32_icache.v",
57 57
 		"lm32_dcache.v", "lm32_top.v", "lm32_debug.v", "lm32_jtag.v", "jtag_cores.v",
58  
-		"jtag_tap_spartan6.v")
  58
+		"jtag_tap_spartan6.v", "lm32_itlb.v", "lm32_dtlb.v")
59 59
 	plat.add_sources(os.path.join("verilog", "lm32"), "lm32_config.v")
60 60
 	
61 61
 	plat.build_cmdline(soc.get_fragment(), clock_domains=soc.crg.get_clock_domains())

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