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ddrphy: request wrdata_en/rddata_en at the same time as the command

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commit baba267db67164ea5bbfe1bf556cce1c11da84a0 1 parent 17b2588
Sébastien Bourdeauducq authored February 24, 2012
4  milkymist/dfii/__init__.py
@@ -42,12 +42,12 @@ def get_fragment(self):
42 42
 			),
43 43
 			self.phase.address.eq(self._address.field.r),
44 44
 			self.phase.bank.eq(self._baddress.field.r),
  45
+			self.phase.wrdata_en.eq(self._command.re & self._wren.r),
  46
+			self.phase.rddata_en.eq(self._command.re & self._rden.r),
45 47
 			self.phase.wrdata.eq(self._wrdata.field.r),
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 			self.phase.wrdata_mask.eq(0)
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 		]
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 		sync = [
49  
-			self.phase.wrdata_en.eq(self._command.re & self._wren.r),
50  
-			self.phase.rddata_en.eq(self._command.re & self._rden.r),
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 			If(self.phase.rddata_valid, self._rddata.field.w.eq(self.phase.rddata))
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 		]
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 		return Fragment(comb, sync)
20  verilog/s6ddrphy/s6ddrphy.v
@@ -3,12 +3,12 @@
3 3
  *
4 4
  ************* DATAPATH SIGNALS ***********
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  * Assert dfi_wrdata_en and present the data 
6  
- * on dfi_wrdata_mask/dfi_wrdata one cycle after
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- * a write command. 
  6
+ * on dfi_wrdata_mask/dfi_wrdata in the same
  7
+ * cycle as the write command.
8 8
  *
9  
- * Assert dfi_rddata_en one cycle after a read
  9
+ * Assert dfi_rddata_en in the same cycle as the read
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  * command. The data will come back on dfi_rddata
11  
- * 3 cycles later, along with the assertion of
  11
+ * 4 cycles later, along with the assertion of
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  * dfi_rddata_valid.
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  *
14 14
  * This PHY only supports CAS Latency 3.
@@ -340,22 +340,26 @@ endgenerate
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  * DQ/DQS/DM control
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  */
342 342
 
  343
+reg d_dfi_wrdata_en_p1;
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+always @(posedge sys_clk)
  345
+	d_dfi_wrdata_en_p1 <= dfi_wrdata_en_p1;
  346
+ 
343 347
 reg r_dfi_wrdata_en;
344 348
 always @(posedge clk2x_270)
345  
-	r_dfi_wrdata_en <= dfi_wrdata_en_p1;
  349
+	r_dfi_wrdata_en <= d_dfi_wrdata_en_p1;
346 350
 
347 351
 reg r2_dfi_wrdata_en;
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 always @(posedge clk2x_270)
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 	r2_dfi_wrdata_en <= r_dfi_wrdata_en;
350 354
 
351 355
 assign drive_dqs = r2_dfi_wrdata_en;
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-assign drive_dq = dfi_wrdata_en_p1;
  356
+assign drive_dq = d_dfi_wrdata_en_p1;
353 357
 
354 358
 wire rddata_valid;
355  
-reg [3:0] rddata_sr;
  359
+reg [4:0] rddata_sr;
356 360
 assign dfi_rddata_valid_w0 = rddata_sr[0];
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 assign dfi_rddata_valid_w1 = rddata_sr[0];
358 362
 always @(posedge sys_clk)
359  
-	rddata_sr <= {dfi_rddata_en_p0, rddata_sr[3:1]};
  363
+	rddata_sr <= {dfi_rddata_en_p0, rddata_sr[4:1]};
360 364
 
361 365
 endmodule

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