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32-device, 8-bit CSR bus

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commit bb21f7584a34fb8044735a0da697c30d70ee6297 1 parent 1b3edd0
Sébastien Bourdeauducq authored December 17, 2011
2  milkymist/uart/__init__.py
@@ -17,7 +17,7 @@ def __init__(self, csr_addr, clk_freq, baud=115200, break_en_default=Constant(0)
17 17
 			("csr_we", self.bus.we_i),
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 			("csr_di", self.bus.d_i),
19 19
 			("uart_rx", self.rx)],
20  
-			[("csr_addr", Constant(csr_addr, BV(4))),
  20
+			[("csr_addr", Constant(csr_addr, BV(5))),
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 			("clk_freq", clk_freq),
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 			("baud", baud),
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 			("break_en_default", break_en_default)],
16  verilog/uart/uart.v
... ...
@@ -1,6 +1,6 @@
1 1
 /*
2 2
  * Milkymist SoC
3  
- * Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
  3
+ * Copyright (C) 2007, 2008, 2009, 2010, 2011 Sebastien Bourdeauducq
4 4
  *
5 5
  * This program is free software: you can redistribute it and/or modify
6 6
  * it under the terms of the GNU General Public License as published by
@@ -16,7 +16,7 @@
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  */
17 17
 
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 module uart #(
19  
-	parameter csr_addr = 4'h0,
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+	parameter csr_addr = 5'h0,
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 	parameter clk_freq = 100000000,
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 	parameter baud = 115200,
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 	parameter break_en_default = 1'b0
@@ -26,8 +26,8 @@ module uart #(
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 	input [13:0] csr_a,
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 	input csr_we,
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-	input [31:0] csr_di,
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-	output reg [31:0] csr_do,
  29
+	input [7:0] csr_di,
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+	output reg [7:0] csr_do,
31 31
 
32 32
 	output irq,
33 33
 
@@ -67,11 +67,11 @@ assign uart_tx = thru_en ? uart_rx : uart_tx_transceiver;
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 assign break = break_en & break_transceiver;
68 68
 
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 /* CSR interface */
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-wire csr_selected = csr_a[13:10] == csr_addr;
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+wire csr_selected = csr_a[13:9] == csr_addr;
71 71
 
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 assign irq = (tx_event & tx_irq_en) | (rx_event & rx_irq_en);
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-assign tx_data = csr_di[7:0];
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+assign tx_data = csr_di;
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 assign tx_wr = csr_selected & csr_we & (csr_a[2:0] == 3'b000);
76 76
 
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 parameter default_divisor = clk_freq/baud/16;
@@ -111,7 +111,7 @@ always @(posedge sys_clk) begin
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 		if(csr_selected) begin
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 			case(csr_a[2:0])
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 				3'b000: csr_do <= rx_data;
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-				3'b001: csr_do <= divisor;
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+// TODO				3'b001: csr_do <= divisor;
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 				3'b010: csr_do <= {tx_event, rx_event, thre};
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 				3'b011: csr_do <= {thru_en, tx_irq_en, rx_irq_en};
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 				3'b100: csr_do <= {break_en};
@@ -119,7 +119,7 @@ always @(posedge sys_clk) begin
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 			if(csr_we) begin
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 				case(csr_a[2:0])
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 					3'b000:; /* handled by transceiver */
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-					3'b001: divisor <= csr_di[15:0];
  122
+// TODO					3'b001: divisor <= csr_di[15:0];
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 					3'b010: begin
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 						/* write one to clear */
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 						if(csr_di[1])

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