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Common include files

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commit bb798176fc850b690865c2883b81e75158d12cd1 1 parent b6aa40d
Sébastien Bourdeauducq authored May 16, 2012
8  common/csrbase.h
... ...
@@ -0,0 +1,8 @@
  1
+#ifndef __CSRBASE_H
  2
+#define __CSRBASE_H
  3
+
  4
+#define UART_BASE	0xe0000000
  5
+#define DFII_BASE	0xe0000800
  6
+#define ID_BASE		0xe0001000
  7
+
  8
+#endif /* __CSRBASE_H */
0  tools/sfl.h → common/sfl.h
File renamed without changes
2  software/include/base/version.h → common/version.h
... ...
@@ -1,6 +1,6 @@
1 1
 #ifndef __VERSION_H
2 2
 #define __VERSION_H
3 3
 
4  
-#define VERSION "2.0-X"
  4
+#define VERSION "2.0"
5 5
 
6 6
 #endif /* __VERSION_H */
2  software/bios/ddrinit.c
@@ -204,7 +204,7 @@ void memtest(void)
204 204
 
205 205
 int ddrinit(void)
206 206
 {
207  
-	printf("Initializing DDRAM...\n");
  207
+	printf("Initializing DDR SDRAM...\n");
208 208
 	
209 209
 	init_sequence();
210 210
 	CSR_DFII_CONTROL = DFII_CONTROL_SEL|DFII_CONTROL_CKE;
2  software/include.mak
@@ -36,7 +36,7 @@ endif
36 36
 # Toolchain options
37 37
 #
38 38
 INCLUDES_NOLIBC ?= -nostdinc -I$(M2DIR)/software/include/base
39  
-INCLUDES = $(INCLUDES_NOLIBC) -I$(M2DIR)/software/include -I$(M2DIR)/tools
  39
+INCLUDES = $(INCLUDES_NOLIBC) -I$(M2DIR)/software/include -I$(M2DIR)/common
40 40
 ASFLAGS = $(INCLUDES) -nostdinc
41 41
 CFLAGS = -O9 -Wall -Wstrict-prototypes -Wold-style-definition -Wshadow \
42 42
 	 -Wmissing-prototypes -fsigned-char $(INCLUDES)
101  software/include/hw/dfii.h
@@ -19,59 +19,62 @@
19 19
 #define __HW_DFII_H
20 20
 
21 21
 #include <hw/common.h>
  22
+#include <csrbase.h>
22 23
 
23  
-#define CSR_DFII_CONTROL		MMPTR(0xe0000800)
  24
+#define DFII_CSR(x)			MMPTR(DFII_BASE+(x))
24 25
 
25  
-#define DFII_CONTROL_SEL		(0x01)
26  
-#define DFII_CONTROL_CKE		(0x02)
  26
+#define CSR_DFII_CONTROL		DFII_CSR(0x00)
27 27
 
28  
-#define CSR_DFII_COMMAND_P0		MMPTR(0xe0000804)
29  
-#define CSR_DFII_AH_P0			MMPTR(0xe0000808)
30  
-#define CSR_DFII_AL_P0			MMPTR(0xe000080C)
31  
-#define CSR_DFII_BA_P0			MMPTR(0xe0000810)
32  
-#define CSR_DFII_WD0_P0			MMPTR(0xe0000814)
33  
-#define CSR_DFII_WD1_P0			MMPTR(0xe0000818)
34  
-#define CSR_DFII_WD2_P0			MMPTR(0xe000081C)
35  
-#define CSR_DFII_WD3_P0			MMPTR(0xe0000820)
36  
-#define CSR_DFII_WD4_P0			MMPTR(0xe0000824)
37  
-#define CSR_DFII_WD5_P0			MMPTR(0xe0000828)
38  
-#define CSR_DFII_WD6_P0			MMPTR(0xe000082C)
39  
-#define CSR_DFII_WD7_P0			MMPTR(0xe0000830)
40  
-#define CSR_DFII_RD0_P0			MMPTR(0xe0000834)
41  
-#define CSR_DFII_RD1_P0			MMPTR(0xe0000838)
42  
-#define CSR_DFII_RD2_P0			MMPTR(0xe000083C)
43  
-#define CSR_DFII_RD3_P0			MMPTR(0xe0000840)
44  
-#define CSR_DFII_RD4_P0			MMPTR(0xe0000844)
45  
-#define CSR_DFII_RD5_P0			MMPTR(0xe0000848)
46  
-#define CSR_DFII_RD6_P0			MMPTR(0xe000084C)
47  
-#define CSR_DFII_RD7_P0			MMPTR(0xe0000850)
  28
+#define DFII_CONTROL_SEL		0x01
  29
+#define DFII_CONTROL_CKE		0x02
48 30
 
49  
-#define CSR_DFII_COMMAND_P1		MMPTR(0xe0000854)
50  
-#define CSR_DFII_AH_P1			MMPTR(0xe0000858)
51  
-#define CSR_DFII_AL_P1			MMPTR(0xe000085C)
52  
-#define CSR_DFII_BA_P1			MMPTR(0xe0000860)
53  
-#define CSR_DFII_WD0_P1			MMPTR(0xe0000864)
54  
-#define CSR_DFII_WD1_P1			MMPTR(0xe0000868)
55  
-#define CSR_DFII_WD2_P1			MMPTR(0xe000086C)
56  
-#define CSR_DFII_WD3_P1			MMPTR(0xe0000870)
57  
-#define CSR_DFII_WD4_P1			MMPTR(0xe0000874)
58  
-#define CSR_DFII_WD5_P1			MMPTR(0xe0000878)
59  
-#define CSR_DFII_WD6_P1			MMPTR(0xe000087C)
60  
-#define CSR_DFII_WD7_P1			MMPTR(0xe0000880)
61  
-#define CSR_DFII_RD0_P1			MMPTR(0xe0000884)
62  
-#define CSR_DFII_RD1_P1			MMPTR(0xe0000888)
63  
-#define CSR_DFII_RD2_P1			MMPTR(0xe000088C)
64  
-#define CSR_DFII_RD3_P1			MMPTR(0xe0000890)
65  
-#define CSR_DFII_RD4_P1			MMPTR(0xe0000894)
66  
-#define CSR_DFII_RD5_P1			MMPTR(0xe0000898)
67  
-#define CSR_DFII_RD6_P1			MMPTR(0xe000089C)
68  
-#define CSR_DFII_RD7_P1			MMPTR(0xe00008a0)
  31
+#define CSR_DFII_COMMAND_P0		DFII_CSR(0x04)
  32
+#define CSR_DFII_AH_P0			DFII_CSR(0x08)
  33
+#define CSR_DFII_AL_P0			DFII_CSR(0x0C)
  34
+#define CSR_DFII_BA_P0			DFII_CSR(0x10)
  35
+#define CSR_DFII_WD0_P0			DFII_CSR(0x14)
  36
+#define CSR_DFII_WD1_P0			DFII_CSR(0x18)
  37
+#define CSR_DFII_WD2_P0			DFII_CSR(0x1C)
  38
+#define CSR_DFII_WD3_P0			DFII_CSR(0x20)
  39
+#define CSR_DFII_WD4_P0			DFII_CSR(0x24)
  40
+#define CSR_DFII_WD5_P0			DFII_CSR(0x28)
  41
+#define CSR_DFII_WD6_P0			DFII_CSR(0x2C)
  42
+#define CSR_DFII_WD7_P0			DFII_CSR(0x30)
  43
+#define CSR_DFII_RD0_P0			DFII_CSR(0x34)
  44
+#define CSR_DFII_RD1_P0			DFII_CSR(0x38)
  45
+#define CSR_DFII_RD2_P0			DFII_CSR(0x3C)
  46
+#define CSR_DFII_RD3_P0			DFII_CSR(0x40)
  47
+#define CSR_DFII_RD4_P0			DFII_CSR(0x44)
  48
+#define CSR_DFII_RD5_P0			DFII_CSR(0x48)
  49
+#define CSR_DFII_RD6_P0			DFII_CSR(0x4C)
  50
+#define CSR_DFII_RD7_P0			DFII_CSR(0x50)
69 51
 
70  
-#define DFII_COMMAND_CS			(0x01)
71  
-#define DFII_COMMAND_WE			(0x02)
72  
-#define DFII_COMMAND_CAS		(0x04)
73  
-#define DFII_COMMAND_RAS		(0x08)
74  
-#define DFII_COMMAND_WRDATA		(0x10)
75  
-#define DFII_COMMAND_RDDATA		(0x20)
  52
+#define CSR_DFII_COMMAND_P1		DFII_CSR(0x54)
  53
+#define CSR_DFII_AH_P1			DFII_CSR(0x58)
  54
+#define CSR_DFII_AL_P1			DFII_CSR(0x5C)
  55
+#define CSR_DFII_BA_P1			DFII_CSR(0x60)
  56
+#define CSR_DFII_WD0_P1			DFII_CSR(0x64)
  57
+#define CSR_DFII_WD1_P1			DFII_CSR(0x68)
  58
+#define CSR_DFII_WD2_P1			DFII_CSR(0x6C)
  59
+#define CSR_DFII_WD3_P1			DFII_CSR(0x70)
  60
+#define CSR_DFII_WD4_P1			DFII_CSR(0x74)
  61
+#define CSR_DFII_WD5_P1			DFII_CSR(0x78)
  62
+#define CSR_DFII_WD6_P1			DFII_CSR(0x7C)
  63
+#define CSR_DFII_WD7_P1			DFII_CSR(0x80)
  64
+#define CSR_DFII_RD0_P1			DFII_CSR(0x84)
  65
+#define CSR_DFII_RD1_P1			DFII_CSR(0x88)
  66
+#define CSR_DFII_RD2_P1			DFII_CSR(0x8C)
  67
+#define CSR_DFII_RD3_P1			DFII_CSR(0x90)
  68
+#define CSR_DFII_RD4_P1			DFII_CSR(0x94)
  69
+#define CSR_DFII_RD5_P1			DFII_CSR(0x98)
  70
+#define CSR_DFII_RD6_P1			DFII_CSR(0x9C)
  71
+#define CSR_DFII_RD7_P1			DFII_CSR(0xA0)
  72
+
  73
+#define DFII_COMMAND_CS			0x01
  74
+#define DFII_COMMAND_WE			0x02
  75
+#define DFII_COMMAND_CAS		0x04
  76
+#define DFII_COMMAND_RAS		0x08
  77
+#define DFII_COMMAND_WRDATA		0x10
  78
+#define DFII_COMMAND_RDDATA		0x20
76 79
 
77 80
 #endif /* __HW_DFII_H */
19  software/include/hw/uart.h
@@ -19,16 +19,19 @@
19 19
 #define __HW_UART_H
20 20
 
21 21
 #include <hw/common.h>
  22
+#include <csrbase.h>
22 23
 
23  
-#define CSR_UART_RXTX		MMPTR(0xe0000000)
24  
-#define CSR_UART_DIVISORH	MMPTR(0xe0000004)
25  
-#define CSR_UART_DIVISORL	MMPTR(0xe0000008)
  24
+#define UART_CSR(x)		MMPTR(UART_BASE+(x))
26 25
 
27  
-#define CSR_UART_EV_STAT	MMPTR(0xe000000c)
28  
-#define CSR_UART_EV_PENDING	MMPTR(0xe0000010)
29  
-#define CSR_UART_EV_ENABLE	MMPTR(0xe0000014)
  26
+#define CSR_UART_RXTX		UART_CSR(0x00)
  27
+#define CSR_UART_DIVISORH	UART_CSR(0x04)
  28
+#define CSR_UART_DIVISORL	UART_CSR(0x08)
30 29
 
31  
-#define UART_EV_TX		(0x1)
32  
-#define UART_EV_RX		(0x2)
  30
+#define CSR_UART_EV_STAT	UART_CSR(0x0c)
  31
+#define CSR_UART_EV_PENDING	UART_CSR(0x10)
  32
+#define CSR_UART_EV_ENABLE	UART_CSR(0x14)
  33
+
  34
+#define UART_EV_TX		0x1
  35
+#define UART_EV_RX		0x2
33 36
 
34 37
 #endif /* __HW_UART_H */
2  tools/Makefile
@@ -4,7 +4,7 @@ CC=clang
4 4
 all: $(TARGETS)
5 5
 
6 6
 %: %.c
7  
-	$(CC) -O2 -Wall -I. -s -o $@ $<
  7
+	$(CC) -O2 -Wall -I../common -s -o $@ $<
8 8
 
9 9
 install: mkmmimg flterm
10 10
 	install -d /usr/local/bin

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