Skip to content
Permalink
Browse files
Common include files
  • Loading branch information
Sebastien Bourdeauducq committed May 16, 2012
1 parent b6aa40d commit bb798176fc850b690865c2883b81e75158d12cd1
@@ -0,0 +1,8 @@
#ifndef __CSRBASE_H
#define __CSRBASE_H

#define UART_BASE 0xe0000000
#define DFII_BASE 0xe0000800
#define ID_BASE 0xe0001000

#endif /* __CSRBASE_H */
File renamed without changes.
@@ -1,6 +1,6 @@
#ifndef __VERSION_H
#define __VERSION_H

#define VERSION "2.0-X"
#define VERSION "2.0"

#endif /* __VERSION_H */
@@ -204,7 +204,7 @@ void memtest(void)

int ddrinit(void)
{
printf("Initializing DDRAM...\n");
printf("Initializing DDR SDRAM...\n");

init_sequence();
CSR_DFII_CONTROL = DFII_CONTROL_SEL|DFII_CONTROL_CKE;
@@ -36,7 +36,7 @@ endif
# Toolchain options
#
INCLUDES_NOLIBC ?= -nostdinc -I$(M2DIR)/software/include/base
INCLUDES = $(INCLUDES_NOLIBC) -I$(M2DIR)/software/include -I$(M2DIR)/tools
INCLUDES = $(INCLUDES_NOLIBC) -I$(M2DIR)/software/include -I$(M2DIR)/common
ASFLAGS = $(INCLUDES) -nostdinc
CFLAGS = -O9 -Wall -Wstrict-prototypes -Wold-style-definition -Wshadow \
-Wmissing-prototypes -fsigned-char $(INCLUDES)
@@ -19,59 +19,62 @@
#define __HW_DFII_H

#include <hw/common.h>
#include <csrbase.h>

#define CSR_DFII_CONTROL MMPTR(0xe0000800)
#define DFII_CSR(x) MMPTR(DFII_BASE+(x))

#define DFII_CONTROL_SEL (0x01)
#define DFII_CONTROL_CKE (0x02)
#define CSR_DFII_CONTROL DFII_CSR(0x00)

#define CSR_DFII_COMMAND_P0 MMPTR(0xe0000804)
#define CSR_DFII_AH_P0 MMPTR(0xe0000808)
#define CSR_DFII_AL_P0 MMPTR(0xe000080C)
#define CSR_DFII_BA_P0 MMPTR(0xe0000810)
#define CSR_DFII_WD0_P0 MMPTR(0xe0000814)
#define CSR_DFII_WD1_P0 MMPTR(0xe0000818)
#define CSR_DFII_WD2_P0 MMPTR(0xe000081C)
#define CSR_DFII_WD3_P0 MMPTR(0xe0000820)
#define CSR_DFII_WD4_P0 MMPTR(0xe0000824)
#define CSR_DFII_WD5_P0 MMPTR(0xe0000828)
#define CSR_DFII_WD6_P0 MMPTR(0xe000082C)
#define CSR_DFII_WD7_P0 MMPTR(0xe0000830)
#define CSR_DFII_RD0_P0 MMPTR(0xe0000834)
#define CSR_DFII_RD1_P0 MMPTR(0xe0000838)
#define CSR_DFII_RD2_P0 MMPTR(0xe000083C)
#define CSR_DFII_RD3_P0 MMPTR(0xe0000840)
#define CSR_DFII_RD4_P0 MMPTR(0xe0000844)
#define CSR_DFII_RD5_P0 MMPTR(0xe0000848)
#define CSR_DFII_RD6_P0 MMPTR(0xe000084C)
#define CSR_DFII_RD7_P0 MMPTR(0xe0000850)
#define DFII_CONTROL_SEL 0x01
#define DFII_CONTROL_CKE 0x02

#define CSR_DFII_COMMAND_P1 MMPTR(0xe0000854)
#define CSR_DFII_AH_P1 MMPTR(0xe0000858)
#define CSR_DFII_AL_P1 MMPTR(0xe000085C)
#define CSR_DFII_BA_P1 MMPTR(0xe0000860)
#define CSR_DFII_WD0_P1 MMPTR(0xe0000864)
#define CSR_DFII_WD1_P1 MMPTR(0xe0000868)
#define CSR_DFII_WD2_P1 MMPTR(0xe000086C)
#define CSR_DFII_WD3_P1 MMPTR(0xe0000870)
#define CSR_DFII_WD4_P1 MMPTR(0xe0000874)
#define CSR_DFII_WD5_P1 MMPTR(0xe0000878)
#define CSR_DFII_WD6_P1 MMPTR(0xe000087C)
#define CSR_DFII_WD7_P1 MMPTR(0xe0000880)
#define CSR_DFII_RD0_P1 MMPTR(0xe0000884)
#define CSR_DFII_RD1_P1 MMPTR(0xe0000888)
#define CSR_DFII_RD2_P1 MMPTR(0xe000088C)
#define CSR_DFII_RD3_P1 MMPTR(0xe0000890)
#define CSR_DFII_RD4_P1 MMPTR(0xe0000894)
#define CSR_DFII_RD5_P1 MMPTR(0xe0000898)
#define CSR_DFII_RD6_P1 MMPTR(0xe000089C)
#define CSR_DFII_RD7_P1 MMPTR(0xe00008a0)
#define CSR_DFII_COMMAND_P0 DFII_CSR(0x04)
#define CSR_DFII_AH_P0 DFII_CSR(0x08)
#define CSR_DFII_AL_P0 DFII_CSR(0x0C)
#define CSR_DFII_BA_P0 DFII_CSR(0x10)
#define CSR_DFII_WD0_P0 DFII_CSR(0x14)
#define CSR_DFII_WD1_P0 DFII_CSR(0x18)
#define CSR_DFII_WD2_P0 DFII_CSR(0x1C)
#define CSR_DFII_WD3_P0 DFII_CSR(0x20)
#define CSR_DFII_WD4_P0 DFII_CSR(0x24)
#define CSR_DFII_WD5_P0 DFII_CSR(0x28)
#define CSR_DFII_WD6_P0 DFII_CSR(0x2C)
#define CSR_DFII_WD7_P0 DFII_CSR(0x30)
#define CSR_DFII_RD0_P0 DFII_CSR(0x34)
#define CSR_DFII_RD1_P0 DFII_CSR(0x38)
#define CSR_DFII_RD2_P0 DFII_CSR(0x3C)
#define CSR_DFII_RD3_P0 DFII_CSR(0x40)
#define CSR_DFII_RD4_P0 DFII_CSR(0x44)
#define CSR_DFII_RD5_P0 DFII_CSR(0x48)
#define CSR_DFII_RD6_P0 DFII_CSR(0x4C)
#define CSR_DFII_RD7_P0 DFII_CSR(0x50)

#define DFII_COMMAND_CS (0x01)
#define DFII_COMMAND_WE (0x02)
#define DFII_COMMAND_CAS (0x04)
#define DFII_COMMAND_RAS (0x08)
#define DFII_COMMAND_WRDATA (0x10)
#define DFII_COMMAND_RDDATA (0x20)
#define CSR_DFII_COMMAND_P1 DFII_CSR(0x54)
#define CSR_DFII_AH_P1 DFII_CSR(0x58)
#define CSR_DFII_AL_P1 DFII_CSR(0x5C)
#define CSR_DFII_BA_P1 DFII_CSR(0x60)
#define CSR_DFII_WD0_P1 DFII_CSR(0x64)
#define CSR_DFII_WD1_P1 DFII_CSR(0x68)
#define CSR_DFII_WD2_P1 DFII_CSR(0x6C)
#define CSR_DFII_WD3_P1 DFII_CSR(0x70)
#define CSR_DFII_WD4_P1 DFII_CSR(0x74)
#define CSR_DFII_WD5_P1 DFII_CSR(0x78)
#define CSR_DFII_WD6_P1 DFII_CSR(0x7C)
#define CSR_DFII_WD7_P1 DFII_CSR(0x80)
#define CSR_DFII_RD0_P1 DFII_CSR(0x84)
#define CSR_DFII_RD1_P1 DFII_CSR(0x88)
#define CSR_DFII_RD2_P1 DFII_CSR(0x8C)
#define CSR_DFII_RD3_P1 DFII_CSR(0x90)
#define CSR_DFII_RD4_P1 DFII_CSR(0x94)
#define CSR_DFII_RD5_P1 DFII_CSR(0x98)
#define CSR_DFII_RD6_P1 DFII_CSR(0x9C)
#define CSR_DFII_RD7_P1 DFII_CSR(0xA0)

#define DFII_COMMAND_CS 0x01
#define DFII_COMMAND_WE 0x02
#define DFII_COMMAND_CAS 0x04
#define DFII_COMMAND_RAS 0x08
#define DFII_COMMAND_WRDATA 0x10
#define DFII_COMMAND_RDDATA 0x20

#endif /* __HW_DFII_H */
@@ -19,16 +19,19 @@
#define __HW_UART_H

#include <hw/common.h>
#include <csrbase.h>

#define CSR_UART_RXTX MMPTR(0xe0000000)
#define CSR_UART_DIVISORH MMPTR(0xe0000004)
#define CSR_UART_DIVISORL MMPTR(0xe0000008)
#define UART_CSR(x) MMPTR(UART_BASE+(x))

#define CSR_UART_EV_STAT MMPTR(0xe000000c)
#define CSR_UART_EV_PENDING MMPTR(0xe0000010)
#define CSR_UART_EV_ENABLE MMPTR(0xe0000014)
#define CSR_UART_RXTX UART_CSR(0x00)
#define CSR_UART_DIVISORH UART_CSR(0x04)
#define CSR_UART_DIVISORL UART_CSR(0x08)

#define UART_EV_TX (0x1)
#define UART_EV_RX (0x2)
#define CSR_UART_EV_STAT UART_CSR(0x0c)
#define CSR_UART_EV_PENDING UART_CSR(0x10)
#define CSR_UART_EV_ENABLE UART_CSR(0x14)

#define UART_EV_TX 0x1
#define UART_EV_RX 0x2

#endif /* __HW_UART_H */
@@ -4,7 +4,7 @@ CC=clang
all: $(TARGETS)

%: %.c
$(CC) -O2 -Wall -I. -s -o $@ $<
$(CC) -O2 -Wall -I../common -s -o $@ $<

install: mkmmimg flterm
install -d /usr/local/bin

0 comments on commit bb79817

Please sign in to comment.