Skip to content

HTTPS clone URL

Subversion checkout URL

You can clone with HTTPS or Subversion.

Download ZIP
Browse files

Use RenameClockDomains decorator instead of add_submodule

  • Loading branch information...
commit bf325594eec9fa726e273f3f8db0800f4bcba1b8 1 parent 8e04de5
@sbourdeauducq sbourdeauducq authored
View
5 milkymist/dvisampler/analysis.py
@@ -137,8 +137,9 @@ def __init__(self):
vsync_r.eq(self.vsync)
]
- fifo = AsyncFIFO(layout_len(frame_layout), 512)
- self.add_submodule(fifo, {"write": "pix", "read": "sys"})
+ fifo = RenameClockDomains(AsyncFIFO(layout_len(frame_layout), 512),
+ {"write": "pix", "read": "sys"})
+ self.submodules += fifo
self.comb += [
fifo.we.eq(fifo_stb),
fifo.din.eq(fifo_in.raw_bits()),
View
4 milkymist/dvisampler/chansync.py
@@ -56,8 +56,8 @@ def __init__(self, nchan=3, depth=8):
###
- syncbuffer = _SyncBuffer(layout_len(channel_layout), depth)
- self.add_submodule(syncbuffer, "pix")
+ syncbuffer = RenameClockDomains(_SyncBuffer(layout_len(channel_layout), depth), "pix")
+ self.submodules += syncbuffer
self.comb += [
syncbuffer.din.eq(data_in.raw_bits()),
data_out.raw_bits().eq(syncbuffer.dout)
View
5 milkymist/dvisampler/debug.py
@@ -25,8 +25,9 @@ def __init__(self, pads, asmiport):
self.data0_cap.serdesstrobe.eq(self.clocking.serdesstrobe)
]
- fifo = AsyncFIFO(10, 256)
- self.add_submodule(fifo, {"write": "pix", "read": "sys"})
+ fifo = RenameClockDomains(AsyncFIFO(10, 256),
+ {"write": "pix", "read": "sys"})
+ self.submodules += fifo
self.comb += [
fifo.din.eq(self.data0_cap.d),
fifo.we.eq(1)
View
5 milkymist/framebuffer/lib.py
@@ -128,8 +128,9 @@ def __init__(self):
###
data_width = 2+2*3*bpc_dac
- fifo = AsyncFIFO(data_width, 512)
- self.add_submodule(fifo, {"write": "sys", "read": "vga"})
+ fifo = RenameClockDomains(AsyncFIFO(data_width, 512),
+ {"write": "sys", "read": "vga"})
+ self.submodules += fifo
fifo_in = self.dac.payload
fifo_out = Record(dac_layout)
self.comb += [
View
3  tb/dvisampler/chansync.py
@@ -7,8 +7,7 @@ class TB(Module):
def __init__(self, test_seq_it):
self.test_seq_it = test_seq_it
- self.chansync = ChanSync()
- self.add_submodule(self.chansync, {"pix": "sys"})
+ self.submodules.chansync = RenameClockDomains(ChanSync(), {"pix": "sys"})
self.comb += self.chansync.valid_i.eq(1)
def do_simulation(self, s):
Please sign in to comment.
Something went wrong with that request. Please try again.