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Use RenameClockDomains decorator instead of add_submodule

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commit bf325594eec9fa726e273f3f8db0800f4bcba1b8 1 parent 8e04de5
Sébastien Bourdeauducq authored
5  milkymist/dvisampler/analysis.py
@@ -137,8 +137,9 @@ def __init__(self):
137 137
 			vsync_r.eq(self.vsync)
138 138
 		]
139 139
 
140  
-		fifo = AsyncFIFO(layout_len(frame_layout), 512)
141  
-		self.add_submodule(fifo, {"write": "pix", "read": "sys"})
  140
+		fifo = RenameClockDomains(AsyncFIFO(layout_len(frame_layout), 512),
  141
+			{"write": "pix", "read": "sys"})
  142
+		self.submodules += fifo
142 143
 		self.comb += [
143 144
 			fifo.we.eq(fifo_stb),
144 145
 			fifo.din.eq(fifo_in.raw_bits()),
4  milkymist/dvisampler/chansync.py
@@ -56,8 +56,8 @@ def __init__(self, nchan=3, depth=8):
56 56
 
57 57
 			###
58 58
 		
59  
-			syncbuffer = _SyncBuffer(layout_len(channel_layout), depth)
60  
-			self.add_submodule(syncbuffer, "pix")
  59
+			syncbuffer = RenameClockDomains(_SyncBuffer(layout_len(channel_layout), depth), "pix")
  60
+			self.submodules += syncbuffer
61 61
 			self.comb += [
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 				syncbuffer.din.eq(data_in.raw_bits()),
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 				data_out.raw_bits().eq(syncbuffer.dout)
5  milkymist/dvisampler/debug.py
@@ -25,8 +25,9 @@ def __init__(self, pads, asmiport):
25 25
 			self.data0_cap.serdesstrobe.eq(self.clocking.serdesstrobe)
26 26
 		]
27 27
 
28  
-		fifo = AsyncFIFO(10, 256)
29  
-		self.add_submodule(fifo, {"write": "pix", "read": "sys"})
  28
+		fifo = RenameClockDomains(AsyncFIFO(10, 256),
  29
+			{"write": "pix", "read": "sys"})
  30
+		self.submodules += fifo
30 31
 		self.comb += [
31 32
 			fifo.din.eq(self.data0_cap.d),
32 33
 			fifo.we.eq(1)
5  milkymist/framebuffer/lib.py
@@ -128,8 +128,9 @@ def __init__(self):
128 128
 		###
129 129
 
130 130
 		data_width = 2+2*3*bpc_dac
131  
-		fifo = AsyncFIFO(data_width, 512)
132  
-		self.add_submodule(fifo, {"write": "sys", "read": "vga"})
  131
+		fifo = RenameClockDomains(AsyncFIFO(data_width, 512),
  132
+			{"write": "sys", "read": "vga"})
  133
+		self.submodules += fifo
133 134
 		fifo_in = self.dac.payload
134 135
 		fifo_out = Record(dac_layout)
135 136
 		self.comb += [
3  tb/dvisampler/chansync.py
@@ -7,8 +7,7 @@ class TB(Module):
7 7
 	def __init__(self, test_seq_it):
8 8
 		self.test_seq_it = test_seq_it
9 9
 
10  
-		self.chansync = ChanSync()
11  
-		self.add_submodule(self.chansync, {"pix": "sys"})
  10
+		self.submodules.chansync = RenameClockDomains(ChanSync(), {"pix": "sys"})
12 11
 		self.comb += self.chansync.valid_i.eq(1)
13 12
 
14 13
 	def do_simulation(self, s):

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