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Define clock domains instead of passing extra clocks as regular signals

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commit c86dd3cbefcc282ad59c40dd81c78edcf81f56f5 1 parent 5931c5e
Sébastien Bourdeauducq authored September 11, 2012
2  constraints.py
@@ -15,7 +15,7 @@ def add_vec(signal, pins, iostandard="LVCMOS33", extra=""):
15 15
 		add(crg0.videoin_rst_n, "W17")
16 16
 		add(crg0.flash_rst_n, "P22", extra="SLEW = FAST | DRIVE = 8")
17 17
 		add(crg0.trigger_reset, "AA4")
18  
-		add(crg0.phy_clk, "M20")
  18
+		add(crg0.eth_clk_pad, "M20")
19 19
 		add(crg0.vga_clk_pad, "A11")
20 20
 		
21 21
 		add_vec(norflash0.adr, ["L22", "L20", "K22", "K21", "J19", "H20", "F22",
7  milkymist/framebuffer/__init__.py
@@ -162,7 +162,6 @@ class FIFO(Actor):
162 162
 	def __init__(self):
163 163
 		super().__init__(("dac", Sink, _dac_layout))
164 164
 		
165  
-		self.vga_clk = Signal()
166 165
 		self.vga_hsync_n = Signal()
167 166
 		self.vga_vsync_n = Signal()
168 167
 		self.vga_r = Signal(BV(_bpc_dac))
@@ -178,7 +177,7 @@ def get_fragment(self):
178 177
 			Instance.Output("data_out", BV(data_width)),
179 178
 			Instance.Output("empty", BV(1)),
180 179
 			Instance.Input("read_en", BV(1)),
181  
-			Instance.Input("clk_read", self.vga_clk),
  180
+			Instance.ClockPort("clk_read", "vga"),
182 181
 
183 182
 			Instance.Input("data_in", BV(data_width)),
184 183
 			Instance.Output("full", BV(1)),
@@ -247,10 +246,6 @@ def __init__(self, address, asmiport, simulation=False):
247 246
 		self.bank = csrgen.Bank(fi.actor.get_registers() + self._comp_actor.get_registers(),
248 247
 			address=address)
249 248
 		
250  
-		# VGA clock input
251  
-		if not simulation:
252  
-			self.vga_clk = fifo.actor.vga_clk
253  
-		
254 249
 		# Pads
255 250
 		self.vga_psave_n = Signal()
256 251
 		if not simulation:
16  milkymist/m1crg/__init__.py
@@ -8,6 +8,10 @@ def __init__(self, infreq, outfreq1x):
8 8
 		self.trigger_reset = Signal()
9 9
 		
10 10
 		self.cd_sys = ClockDomain("sys")
  11
+		self.cd_sys2x_270 = ClockDomain("sys2x_270")
  12
+		self.cd_sys4x_wr = ClockDomain("sys4x_wr")
  13
+		self.cd_sys4x_rd = ClockDomain("sys4x_rd")
  14
+		self.cd_vga = ClockDomain("vga")
11 15
 		
12 16
 		ratio = Fraction(outfreq1x)/Fraction(infreq)
13 17
 		in_period = float(Fraction(1000000000)/Fraction(infreq))
@@ -20,20 +24,20 @@ def __init__(self, infreq, outfreq1x):
20 24
 			Instance.Input("trigger_reset", self.trigger_reset),
21 25
 			
22 26
 			Instance.Output("sys_clk", self.cd_sys.clk),
23  
-			Instance.Output("sys_rst", self.cd_sys.rst)
  27
+			Instance.Output("sys_rst", self.cd_sys.rst),
  28
+			Instance.Output("clk2x_270", self.cd_sys2x_270.clk),
  29
+			Instance.Output("clk4x_wr", self.cd_sys4x_wr.clk),
  30
+			Instance.Output("clk4x_rd", self.cd_sys4x_rd.clk),
  31
+			Instance.Output("vga_clk", self.cd_vga.clk)
24 32
 		]
25 33
 		
26 34
 		for name in [
27 35
 			"ac97_rst_n",
28 36
 			"videoin_rst_n",
29 37
 			"flash_rst_n",
30  
-			"clk2x_270",
31  
-			"clk4x_wr",
32 38
 			"clk4x_wr_strb",
33  
-			"clk4x_rd",
34 39
 			"clk4x_rd_strb",
35  
-			"phy_clk",
36  
-			"vga_clk",
  40
+			"eth_clk_pad",
37 41
 			"vga_clk_pad"
38 42
 		]:
39 43
 			s = Signal(name=name)
8  milkymist/s6ddrphy/__init__.py
@@ -7,13 +7,13 @@ def __init__(self, a, ba, d):
7 7
 			Instance.Parameter("NUM_AD", a),
8 8
 			Instance.Parameter("NUM_BA", ba),
9 9
 			Instance.Parameter("NUM_D", d),
10  
-			Instance.ClockPort("sys_clk")
  10
+			Instance.ClockPort("sys_clk"),
  11
+			Instance.ClockPort("clk2x_270", "sys2x_270"),
  12
+			Instance.ClockPort("clk4x_wr", "sys4x_wr"),
  13
+			Instance.ClockPort("clk4x_rd", "sys4x_rd")
11 14
 		]
12 15
 		for name, width, cl in [
13  
-			("clk2x_270", 1, Instance.Input),
14  
-			("clk4x_wr", 1, Instance.Input),
15 16
 			("clk4x_wr_strb", 1, Instance.Input),
16  
-			("clk4x_rd", 1, Instance.Input),
17 17
 			("clk4x_rd_strb", 1, Instance.Input),
18 18
 			
19 19
 			("sd_clk_out_p", 1, Instance.Output),
27  top.py
@@ -46,17 +46,6 @@ def ns(t, margin=True):
46 46
 	write_time=16
47 47
 )
48 48
 
49  
-def ddrphy_clocking(crg, phy):
50  
-	names = [
51  
-		"clk2x_270",
52  
-		"clk4x_wr",
53  
-		"clk4x_wr_strb",
54  
-		"clk4x_rd",
55  
-		"clk4x_rd_strb"
56  
-	]
57  
-	comb = [getattr(phy, name).eq(getattr(crg, name)) for name in names]
58  
-	return Fragment(comb)
59  
-
60 49
 csr_macros = get_macros("common/csrbase.h")
61 50
 def csr_offset(name):
62 51
 	base = int(csr_macros[name + "_BASE"], 0)
@@ -149,18 +138,24 @@ def get():
149 138
 	#
150 139
 	crg0 = m1crg.M1CRG(50*MHz, clk_freq)
151 140
 	
152  
-	vga_clocking = Fragment([
153  
-		fb0.vga_clk.eq(crg0.vga_clk)
  141
+	ddrphy_strobes = Fragment([
  142
+		ddrphy0.clk4x_wr_strb.eq(crg0.clk4x_wr_strb),
  143
+		ddrphy0.clk4x_rd_strb.eq(crg0.clk4x_rd_strb)
154 144
 	])
155 145
 	frag = autofragment.from_local() \
156 146
 		+ interrupts \
157  
-		+ ddrphy_clocking(crg0, ddrphy0) \
158  
-		+ vga_clocking
  147
+		+ ddrphy_strobes
159 148
 	cst = Constraints(crg0, norflash0, uart0, ddrphy0, minimac0, fb0)
160 149
 	src_verilog, vns = verilog.convert(frag,
161 150
 		cst.get_ios(),
162 151
 		name="soc",
163  
-		clock_domains={"sys": crg0.cd_sys},
  152
+		clock_domains={
  153
+			"sys": crg0.cd_sys,
  154
+			"sys2x_270": crg0.cd_sys2x_270,
  155
+			"sys4x_wr": crg0.cd_sys4x_wr,
  156
+			"sys4x_rd": crg0.cd_sys4x_rd,
  157
+			"vga": crg0.cd_vga
  158
+		},
164 159
 		return_ns=True)
165 160
 	src_ucf = cst.get_ucf(vns)
166 161
 	return (src_verilog, src_ucf)
4  verilog/m1crg/m1crg.v
@@ -23,7 +23,7 @@ module m1crg #(
23 23
 	output clk4x_rd_strb,
24 24
 	
25 25
 	/* Ethernet PHY clock */
26  
-	output reg phy_clk,	/* < unbuffered, to I/O */
  26
+	output reg eth_clk_pad,	/* < unbuffered, to I/O */
27 27
 	
28 28
 	/* VGA clock */
29 29
 	output vga_clk,		/* < buffered, to internal clock network */
@@ -193,7 +193,7 @@ BUFG bufg_x1(
193 193
 
194 194
 /* Ethernet PHY */
195 195
 always @(posedge pllout4)
196  
-	phy_clk <= ~phy_clk;
  196
+	eth_clk_pad <= ~eth_clk_pad;
197 197
 
198 198
 /* VGA clock */
199 199
 // TODO: hook up the reprogramming interface

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