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Define clock domains instead of passing extra clocks as regular signals
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Sebastien Bourdeauducq committed Sep 10, 2012
1 parent 5931c5e commit c86dd3cbefcc282ad59c40dd81c78edcf81f56f5
Showing with 29 additions and 35 deletions.
  1. +1 −1 constraints.py
  2. +1 −6 milkymist/framebuffer/__init__.py
  3. +10 −6 milkymist/m1crg/__init__.py
  4. +4 −4 milkymist/s6ddrphy/__init__.py
  5. +11 −16 top.py
  6. +2 −2 verilog/m1crg/m1crg.v
@@ -15,7 +15,7 @@ def add_vec(signal, pins, iostandard="LVCMOS33", extra=""):
add(crg0.videoin_rst_n, "W17")
add(crg0.flash_rst_n, "P22", extra="SLEW = FAST | DRIVE = 8")
add(crg0.trigger_reset, "AA4")
add(crg0.phy_clk, "M20")
add(crg0.eth_clk_pad, "M20")
add(crg0.vga_clk_pad, "A11")

add_vec(norflash0.adr, ["L22", "L20", "K22", "K21", "J19", "H20", "F22",
@@ -162,7 +162,6 @@ class FIFO(Actor):
def __init__(self):
super().__init__(("dac", Sink, _dac_layout))

self.vga_clk = Signal()
self.vga_hsync_n = Signal()
self.vga_vsync_n = Signal()
self.vga_r = Signal(BV(_bpc_dac))
@@ -178,7 +177,7 @@ def get_fragment(self):
Instance.Output("data_out", BV(data_width)),
Instance.Output("empty", BV(1)),
Instance.Input("read_en", BV(1)),
Instance.Input("clk_read", self.vga_clk),
Instance.ClockPort("clk_read", "vga"),

Instance.Input("data_in", BV(data_width)),
Instance.Output("full", BV(1)),
@@ -247,10 +246,6 @@ def __init__(self, address, asmiport, simulation=False):
self.bank = csrgen.Bank(fi.actor.get_registers() + self._comp_actor.get_registers(),
address=address)

# VGA clock input
if not simulation:
self.vga_clk = fifo.actor.vga_clk

# Pads
self.vga_psave_n = Signal()
if not simulation:
@@ -8,6 +8,10 @@ def __init__(self, infreq, outfreq1x):
self.trigger_reset = Signal()

self.cd_sys = ClockDomain("sys")
self.cd_sys2x_270 = ClockDomain("sys2x_270")
self.cd_sys4x_wr = ClockDomain("sys4x_wr")
self.cd_sys4x_rd = ClockDomain("sys4x_rd")
self.cd_vga = ClockDomain("vga")

ratio = Fraction(outfreq1x)/Fraction(infreq)
in_period = float(Fraction(1000000000)/Fraction(infreq))
@@ -20,20 +24,20 @@ def __init__(self, infreq, outfreq1x):
Instance.Input("trigger_reset", self.trigger_reset),

Instance.Output("sys_clk", self.cd_sys.clk),
Instance.Output("sys_rst", self.cd_sys.rst)
Instance.Output("sys_rst", self.cd_sys.rst),
Instance.Output("clk2x_270", self.cd_sys2x_270.clk),
Instance.Output("clk4x_wr", self.cd_sys4x_wr.clk),
Instance.Output("clk4x_rd", self.cd_sys4x_rd.clk),
Instance.Output("vga_clk", self.cd_vga.clk)
]

for name in [
"ac97_rst_n",
"videoin_rst_n",
"flash_rst_n",
"clk2x_270",
"clk4x_wr",
"clk4x_wr_strb",
"clk4x_rd",
"clk4x_rd_strb",
"phy_clk",
"vga_clk",
"eth_clk_pad",
"vga_clk_pad"
]:
s = Signal(name=name)
@@ -7,13 +7,13 @@ def __init__(self, a, ba, d):
Instance.Parameter("NUM_AD", a),
Instance.Parameter("NUM_BA", ba),
Instance.Parameter("NUM_D", d),
Instance.ClockPort("sys_clk")
Instance.ClockPort("sys_clk"),
Instance.ClockPort("clk2x_270", "sys2x_270"),
Instance.ClockPort("clk4x_wr", "sys4x_wr"),
Instance.ClockPort("clk4x_rd", "sys4x_rd")
]
for name, width, cl in [
("clk2x_270", 1, Instance.Input),
("clk4x_wr", 1, Instance.Input),
("clk4x_wr_strb", 1, Instance.Input),
("clk4x_rd", 1, Instance.Input),
("clk4x_rd_strb", 1, Instance.Input),

("sd_clk_out_p", 1, Instance.Output),
27 top.py
@@ -46,17 +46,6 @@ def ns(t, margin=True):
write_time=16
)

def ddrphy_clocking(crg, phy):
names = [
"clk2x_270",
"clk4x_wr",
"clk4x_wr_strb",
"clk4x_rd",
"clk4x_rd_strb"
]
comb = [getattr(phy, name).eq(getattr(crg, name)) for name in names]
return Fragment(comb)

csr_macros = get_macros("common/csrbase.h")
def csr_offset(name):
base = int(csr_macros[name + "_BASE"], 0)
@@ -149,18 +138,24 @@ def get():
#
crg0 = m1crg.M1CRG(50*MHz, clk_freq)

vga_clocking = Fragment([
fb0.vga_clk.eq(crg0.vga_clk)
ddrphy_strobes = Fragment([
ddrphy0.clk4x_wr_strb.eq(crg0.clk4x_wr_strb),
ddrphy0.clk4x_rd_strb.eq(crg0.clk4x_rd_strb)
])
frag = autofragment.from_local() \
+ interrupts \
+ ddrphy_clocking(crg0, ddrphy0) \
+ vga_clocking
+ ddrphy_strobes
cst = Constraints(crg0, norflash0, uart0, ddrphy0, minimac0, fb0)
src_verilog, vns = verilog.convert(frag,
cst.get_ios(),
name="soc",
clock_domains={"sys": crg0.cd_sys},
clock_domains={
"sys": crg0.cd_sys,
"sys2x_270": crg0.cd_sys2x_270,
"sys4x_wr": crg0.cd_sys4x_wr,
"sys4x_rd": crg0.cd_sys4x_rd,
"vga": crg0.cd_vga
},
return_ns=True)
src_ucf = cst.get_ucf(vns)
return (src_verilog, src_ucf)
@@ -23,7 +23,7 @@ module m1crg #(
output clk4x_rd_strb,

/* Ethernet PHY clock */
output reg phy_clk, /* < unbuffered, to I/O */
output reg eth_clk_pad, /* < unbuffered, to I/O */

/* VGA clock */
output vga_clk, /* < buffered, to internal clock network */
@@ -193,7 +193,7 @@ BUFG bufg_x1(

/* Ethernet PHY */
always @(posedge pllout4)
phy_clk <= ~phy_clk;
eth_clk_pad <= ~eth_clk_pad;

/* VGA clock */
// TODO: hook up the reprogramming interface

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