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s6ddrphy: DQ/DQS/DM SERDES

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commit cbc3b7fa834c52ef435bc93f63130c48107ff39b 1 parent 4c1e18a
Sébastien Bourdeauducq authored February 20, 2012

Showing 1 changed file with 174 additions and 4 deletions. Show diff stats Hide diff stats

  1. 178  verilog/s6ddrphy/s6ddrphy.v
178  verilog/s6ddrphy/s6ddrphy.v
@@ -182,9 +182,179 @@ always @(posedge clk2x_90) begin
182 182
 	end
183 183
 end
184 184
 
185  
-// TODO
186  
-assign sd_dq = 32'hzzzzzzzz;
187  
-assign sd_dm = 0;
188  
-assign sd_dqs = 4'hz;
  185
+/* 
  186
+ * DQ/DQS/DM data
  187
+ */
  188
+
  189
+genvar i;
  190
+
  191
+wire drive_dqs;
  192
+wire [NUM_D/16-1:0] dqs_o;
  193
+wire [NUM_D/16-1:0] dqs_t;
  194
+generate
  195
+	for(i=0;i<NUM_D/16;i=i+1)
  196
+	begin: gen_dqs
  197
+		ODDR2 #(
  198
+			.DDR_ALIGNMENT("C0"),
  199
+			.INIT(1'b0),
  200
+			.SRTYPE("ASYNC")
  201
+		) dqs_o_oddr (
  202
+			.Q(dqs_o[i]),
  203
+			.C0(clk2x_90),
  204
+			.C1(~clk2x_90),
  205
+			.CE(1'b1),
  206
+			.D0(1'b0),
  207
+			.D1(1'b1),
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+			.R(1'b0),
  209
+			.S(1'b0)
  210
+		);
  211
+		ODDR2 #(
  212
+			.DDR_ALIGNMENT("C0"),
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+			.INIT(1'b0),
  214
+			.SRTYPE("ASYNC")
  215
+		) dqs_t_oddr (
  216
+			.Q(dqs_t[i]),
  217
+			.C0(clk2x_90),
  218
+			.C1(~clk2x_90),
  219
+			.CE(1'b1),
  220
+			.D0(~drive_dqs),
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+			.D1(~drive_dqs),
  222
+			.R(1'b0),
  223
+			.S(1'b0)
  224
+		);
  225
+		OBUFT dqs_obuft(
  226
+			.I(dqs_o[i]),
  227
+			.T(dqs_t[i]),
  228
+			.O(sd_dqs[i])
  229
+		);
  230
+	end
  231
+endgenerate
  232
+
  233
+wire drive_dq;
  234
+wire [NUM_D/2-1:0] dq_i;
  235
+wire [NUM_D/2-1:0] dq_o;
  236
+wire [NUM_D/2-1:0] dq_t;
  237
+generate
  238
+	for(i=0;i<NUM_D/2;i=i+1)
  239
+	begin: gen_dq
  240
+		OSERDES2 #(
  241
+			.DATA_WIDTH(4),
  242
+			.DATA_RATE_OQ("SDR"),
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+			.DATA_RATE_OT("SDR"),
  244
+			.SERDES_MODE("NONE"),
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+			.OUTPUT_MODE("SINGLE_ENDED")
  246
+		) dq_oserdes (
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+			.OQ(dq_o[i]),
  248
+			.OCE(1'b1),
  249
+			.CLK0(clk4x_wr),
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+			.CLK1(1'b0),
  251
+			.IOCE(clk4x_wr_strb),
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+			.RST(),
  253
+			.CLKDIV(sys_clk),
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+			.D1(dfi_wrdata_p0[2*i]),
  255
+			.D2(dfi_wrdata_p0[2*i+1]),
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+			.D3(dfi_wrdata_p1[2*i]),
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+			.D4(dfi_wrdata_p1[2*i+1]),
  258
+			.TQ(dq_t[i]),
  259
+			.T1(~drive_dq),
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+			.T2(~drive_dq),
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+			.T3(~drive_dq),
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+			.T4(~drive_dq),
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+			.TRAIN(1'b0),
  264
+			.TCE(1'b1),
  265
+			.SHIFTIN1(1'b0),
  266
+			.SHIFTIN2(1'b0),
  267
+			.SHIFTIN3(1'b0),
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+			.SHIFTIN4(1'b0),
  269
+			.SHIFTOUT1(),
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+			.SHIFTOUT2(),
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+			.SHIFTOUT3(),
  272
+			.SHIFTOUT4()
  273
+		);
  274
+		ISERDES2 #(
  275
+			.DATA_WIDTH(4),
  276
+			.DATA_RATE("SDR"),
  277
+			.BITSLIP_ENABLE("FALSE"),
  278
+			.SERDES_MODE("NONE"),
  279
+			.INTERFACE_TYPE("RETIMED")
  280
+		) dq_iserdes (
  281
+			.D(dq_i[i]),
  282
+			.CE0(1'b1),
  283
+			.CLK0(clk4x_rd),
  284
+			.CLK1(1'b0),
  285
+			.IOCE(clk4x_rd_strb),
  286
+			.RST(),
  287
+			.CLKDIV(clk),
  288
+			.SHIFTIN(),
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+			.BITSLIP(1'b0),
  290
+			.FABRICOUT(),
  291
+			.Q1(dfi_rddata_w0[2*i]),
  292
+			.Q2(dfi_rddata_w0[2*i+1]),
  293
+			.Q3(dfi_rddata_w1[2*i]),
  294
+			.Q4(dfi_rddata_w1[2*i+1]),
  295
+			.DFB(),
  296
+			.CFB0(),
  297
+			.CFB1(),
  298
+			.VALID(),
  299
+			.INCDEC(),
  300
+			.SHIFTOUT()
  301
+		);
  302
+		IOBUF dq_iobuf(
  303
+			.I(dq_o[i]),
  304
+			.O(dq_i[i]),
  305
+			.T(dq_t[i]),
  306
+			.IO(sd_dq[i])
  307
+		);
  308
+	end
  309
+endgenerate
  310
+
  311
+generate
  312
+	for(i=0;i<NUM_D/16;i=i+1)
  313
+	begin: gen_dm_oserdes
  314
+		OSERDES2 #(
  315
+			.DATA_WIDTH(4),
  316
+			.DATA_RATE_OQ("SDR"),
  317
+			.DATA_RATE_OT("SDR"),
  318
+			.SERDES_MODE("NONE"),
  319
+			.OUTPUT_MODE("SINGLE_ENDED")
  320
+		) dm_oserdes (
  321
+			.OQ(sd_dm[i]),
  322
+			.OCE(1'b1),
  323
+			.CLK0(clk4x_wr),
  324
+			.CLK1(1'b0),
  325
+			.IOCE(clk4x_wr_strb),
  326
+			.RST(),
  327
+			.CLKDIV(sys_clk),
  328
+			.D1(dfi_wrdata_mask_p0[2*i]),
  329
+			.D2(dfi_wrdata_mask_p0[2*i+1]),
  330
+			.D3(dfi_wrdata_mask_p1[2*i]),
  331
+			.D4(dfi_wrdata_mask_p1[2*i+1]),
  332
+			.TQ(),
  333
+			.T1(),
  334
+			.T2(),
  335
+			.T3(),
  336
+			.T4(),
  337
+			.TRAIN(1'b0),
  338
+			.TCE(1'b0),
  339
+			.SHIFTIN1(1'b0),
  340
+			.SHIFTIN2(1'b0),
  341
+			.SHIFTIN3(1'b0),
  342
+			.SHIFTIN4(1'b0),
  343
+			.SHIFTOUT1(),
  344
+			.SHIFTOUT2(),
  345
+			.SHIFTOUT3(),
  346
+			.SHIFTOUT4()
  347
+		);
  348
+	end
  349
+endgenerate
189 350
  
  351
+/* 
  352
+ * DQ/DQS/DM control
  353
+ */
  354
+
  355
+// TODO
  356
+
  357
+assign drive_dqs = 0;
  358
+assign drive_dq = 0;
  359
+
190 360
 endmodule

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