liteeth_mini: remove phy.dw parameterization. (fixes #70)

misoc/cores/liteeth_mini/common.py

@@ -6,7 +6,7 @@
 eth_preamble = 0xD555555555555555
 
 
-def eth_phy_layout(dw):
+def eth_phy_layout(dw=8):
     return [
         ("data", dw),
         ("last_be", dw//8),

misoc/cores/liteeth_mini/mac/core.py

@@ -11,14 +11,11 @@ class LiteEthMACCore(Module, AutoCSR):
     def __init__(self, phy, dw, endianness="big",
             with_preamble_crc=True,
             with_padding=True):
-        if dw < phy.dw:
-            raise ValueError("Core data width({}) must be larger than PHY data width({})".format(dw, phy.dw))
-
         rx_pipeline = [phy]
         tx_pipeline = [phy]
 
         # Interpacket gap
-        tx_gap_inserter = gap.LiteEthMACGap(phy.dw)
+        tx_gap_inserter = gap.LiteEthMACGap()
         self.submodules += ClockDomainsRenamer("eth_tx")(tx_gap_inserter)
         tx_pipeline += [tx_gap_inserter]
 
@@ -29,14 +26,14 @@ def __init__(self, phy, dw, endianness="big",
             self.crc_errors = CSRStatus(32)
 
             # Preamble insert/check
-            preamble_inserter = preamble.LiteEthMACPreambleInserter(phy.dw)
-            preamble_checker = preamble.LiteEthMACPreambleChecker(phy.dw)
+            preamble_inserter = preamble.LiteEthMACPreambleInserter()
+            preamble_checker = preamble.LiteEthMACPreambleChecker()
             self.submodules += ClockDomainsRenamer("eth_tx")(preamble_inserter)
             self.submodules += ClockDomainsRenamer("eth_rx")(preamble_checker)
 
             # CRC insert/check
-            crc32_inserter = crc.LiteEthMACCRC32Inserter(eth_phy_layout(phy.dw))
-            crc32_checker = crc.LiteEthMACCRC32Checker(eth_phy_layout(phy.dw))
+            crc32_inserter = crc.LiteEthMACCRC32Inserter(eth_phy_layout(8))
+            crc32_checker = crc.LiteEthMACCRC32Checker(eth_phy_layout(8))
             self.submodules += ClockDomainsRenamer("eth_tx")(crc32_inserter)
             self.submodules += ClockDomainsRenamer("eth_rx")(crc32_checker)
 
@@ -60,31 +57,30 @@ def __init__(self, phy, dw, endianness="big",
 
         # Padding
         if with_padding:
-            padding_inserter = padding.LiteEthMACPaddingInserter(phy.dw, 60)
-            padding_checker = padding.LiteEthMACPaddingChecker(phy.dw, 60)
+            padding_inserter = padding.LiteEthMACPaddingInserter(60)
+            padding_checker = padding.LiteEthMACPaddingChecker(60)
             self.submodules += ClockDomainsRenamer("eth_tx")(padding_inserter)
             self.submodules += ClockDomainsRenamer("eth_rx")(padding_checker)
 
             tx_pipeline += [padding_inserter]
             rx_pipeline += [padding_checker]
 
-        # Delimiters
         if dw != 8:
-            tx_last_be = last_be.LiteEthMACTXLastBE(phy.dw)
-            rx_last_be = last_be.LiteEthMACRXLastBE(phy.dw)
+            # Delimiters
+            tx_last_be = last_be.LiteEthMACTXLastBE()
+            rx_last_be = last_be.LiteEthMACRXLastBE()
             self.submodules += ClockDomainsRenamer("eth_tx")(tx_last_be)
             self.submodules += ClockDomainsRenamer("eth_rx")(rx_last_be)
 
             tx_pipeline += [tx_last_be]
             rx_pipeline += [rx_last_be]
 
-        # Converters
-        if dw != phy.dw:
+            # Converters
             reverse = endianness == "big"
             tx_converter = stream.StrideConverter(eth_phy_layout(dw),
-                                     eth_phy_layout(phy.dw),
+                                     eth_phy_layout(8),
                                      reverse=reverse)
-            rx_converter = stream.StrideConverter(eth_phy_layout(phy.dw),
+            rx_converter = stream.StrideConverter(eth_phy_layout(8),
                                      eth_phy_layout(dw),
                                      reverse=reverse)
             self.submodules += ClockDomainsRenamer("eth_tx")(tx_converter)

misoc/cores/liteeth_mini/mac/gap.py

@@ -8,14 +8,13 @@
 
 
 class LiteEthMACGap(Module):
-    def __init__(self, dw):
-        self.sink = sink = stream.Endpoint(eth_phy_layout(dw))
-        self.source = source = stream.Endpoint(eth_phy_layout(dw))
+    def __init__(self):
+        self.sink = sink = stream.Endpoint(eth_phy_layout(8))
+        self.source = source = stream.Endpoint(eth_phy_layout(8))
 
         # # #
 
-        gap = math.ceil(eth_interpacket_gap/(dw//8))
-        counter = Signal(max=gap)
+        counter = Signal(max=eth_interpacket_gap)
         counter_reset = Signal()
         counter_ce = Signal()
         self.sync += \
@@ -35,7 +34,7 @@ def __init__(self, dw):
         )
         fsm.act("GAP",
             counter_ce.eq(1),
-            If(counter == (gap-1),
+            If(counter == eth_interpacket_gap - 1,
                 NextState("COPY")
             )
         )

misoc/cores/liteeth_mini/mac/last_be.py

@@ -5,9 +5,9 @@
 
 
 class LiteEthMACTXLastBE(Module):
-    def __init__(self, dw):
-        self.sink = sink = stream.Endpoint(eth_phy_layout(dw))
-        self.source = source = stream.Endpoint(eth_phy_layout(dw))
+    def __init__(self):
+        self.sink = sink = stream.Endpoint(eth_phy_layout(8))
+        self.source = source = stream.Endpoint(eth_phy_layout(8))
 
         # # #
 
@@ -29,9 +29,9 @@ def __init__(self, dw):
 
 
 class LiteEthMACRXLastBE(Module):
-    def __init__(self, dw):
-        self.sink = sink = stream.Endpoint(eth_phy_layout(dw))
-        self.source = source = stream.Endpoint(eth_phy_layout(dw))
+    def __init__(self):
+        self.sink = sink = stream.Endpoint(eth_phy_layout(8))
+        self.source = source = stream.Endpoint(eth_phy_layout(8))
 
         # # #
 

misoc/cores/liteeth_mini/mac/padding.py

@@ -7,14 +7,12 @@
 
 
 class LiteEthMACPaddingInserter(Module):
-    def __init__(self, dw, padding):
-        self.sink = sink = stream.Endpoint(eth_phy_layout(dw))
-        self.source = source = stream.Endpoint(eth_phy_layout(dw))
+    def __init__(self, padding):
+        self.sink = sink = stream.Endpoint(eth_phy_layout(8))
+        self.source = source = stream.Endpoint(eth_phy_layout(8))
 
         # # #
 
-        padding_limit = math.ceil(padding/(dw/8))-1
-
         counter = Signal(16, reset=1)
         counter_done = Signal()
         counter_reset = Signal()
@@ -25,7 +23,7 @@ def __init__(self, dw, padding):
             ).Elif(counter_ce,
                 counter.eq(counter + 1)
             )
-        self.comb += counter_done.eq(counter >= padding_limit)
+        self.comb += counter_done.eq(counter >= padding-1)
 
         self.submodules.fsm = fsm = FSM(reset_state="IDLE")
         fsm.act("IDLE",
@@ -57,9 +55,9 @@ def __init__(self, dw, padding):
 
 
 class LiteEthMACPaddingChecker(Module):
-    def __init__(self, dw, packet_min_length):
-        self.sink = sink = stream.Endpoint(eth_phy_layout(dw))
-        self.source = source = stream.Endpoint(eth_phy_layout(dw))
+    def __init__(self, packet_min_length):
+        self.sink = sink = stream.Endpoint(eth_phy_layout(8))
+        self.source = source = stream.Endpoint(eth_phy_layout(8))
 
         # # #
 

misoc/cores/liteeth_mini/mac/preamble.py

@@ -19,15 +19,14 @@ class LiteEthMACPreambleInserter(Module):
     source : out
         Preamble, SFD, and packet octets.
     """
-    def __init__(self, dw):
-        self.sink = sink = stream.Endpoint(eth_phy_layout(dw))
-        self.source = source = stream.Endpoint(eth_phy_layout(dw))
+    def __init__(self):
+        self.sink = sink = stream.Endpoint(eth_phy_layout(8))
+        self.source = source = stream.Endpoint(eth_phy_layout(8))
 
         # # #
 
         preamble = Signal(64, reset=eth_preamble)
-        cnt_max = (64//dw)-1
-        cnt = Signal(max=cnt_max+1)
+        cnt = Signal(max=8)
         clr_cnt = Signal()
         inc_cnt = Signal()
 
@@ -51,7 +50,7 @@ def __init__(self, dw):
         fsm.act("INSERT",
             source.stb.eq(1),
             chooser(preamble, cnt, source.data),
-            If(cnt == cnt_max,
+            If(cnt == 7,
                 If(source.ack, NextState("COPY"))
             ).Else(
                 inc_cnt.eq(source.ack)
@@ -85,10 +84,9 @@ class LiteEthMACPreambleChecker(Module):
     error : out
         Pulses every time a preamble error is detected.
     """
-    def __init__(self, dw):
-        assert dw == 8
-        self.sink = sink = stream.Endpoint(eth_phy_layout(dw))
-        self.source = source = stream.Endpoint(eth_phy_layout(dw))
+    def __init__(self):
+        self.sink = sink = stream.Endpoint(eth_phy_layout(8))
+        self.source = source = stream.Endpoint(eth_phy_layout(8))
 
         self.error = Signal()
 

misoc/cores/liteeth_mini/phy/a7_1000basex.py

@@ -37,7 +37,6 @@ def __init__(self, qpll_channel, data_pads, sys_clk_freq):
         pcs = PCS(lsb_first=True)
         self.submodules += pcs
 
-        self.dw = 8
         self.sink = pcs.sink
         self.source = pcs.source
         self.link_up = pcs.link_up

misoc/cores/liteeth_mini/phy/gmii.py

@@ -69,7 +69,6 @@ def __init__(self, clock_pads, pads, mii_mode=0):
 
 class LiteEthPHYGMII(Module, AutoCSR):
     def __init__(self, clock_pads, pads):
-        self.dw = 8
         self.submodules.crg = LiteEthPHYGMIICRG(clock_pads, pads)
         self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYGMIITX(pads))
         self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYGMIIRX(pads))

misoc/cores/liteeth_mini/phy/gmii_mii.py

@@ -161,7 +161,6 @@ def __init__(self, clk_freq):
 
 class LiteEthPHYGMIIMII(Module, AutoCSR):
     def __init__(self, clock_pads, pads, clk_freq):
-        self.dw = 8
         # Note: we can use GMII CRG since it also handles tx clock pad used for MII
         self.submodules.mode_detection = LiteEthGMIIMIIModeDetection(clk_freq)
         mode = self.mode_detection.mode

misoc/cores/liteeth_mini/phy/mii.py

@@ -73,7 +73,6 @@ def __init__(self, clock_pads, pads):
 
 class LiteEthPHYMII(Module, AutoCSR):
     def __init__(self, clock_pads, pads):
-        self.dw = 8
         self.submodules.crg = LiteEthPHYMIICRG(clock_pads, pads)
         self.submodules.tx =  ClockDomainsRenamer("eth_tx")(LiteEthPHYMIITX(pads))
         self.submodules.rx = ClockDomainsRenamer("eth_tx")(LiteEthPHYMIIRX(pads))

misoc/cores/liteeth_mini/phy/rgmii.py

@@ -70,7 +70,6 @@ def __init__(self, clock_pads, pads):
 
 class LiteEthPHYRGMII(Module, AutoCSR):
     def __init__(self, clock_pads, pads):
-        self.dw = 8
         self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads, pads)
         self.submodules.tx = LiteEthPHYRGMIITX(pads)
         self.submodules.rx = LiteEthPHYRGMIIRX(pads)