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s6ddrphy: use single-ended DQS

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commit cdd58e023b1a9fe1ebaf02c49cd0f861aaa93ba6 1 parent cc5e4ae
Sébastien Bourdeauducq authored February 17, 2012

Showing 1 changed file with 27 additions and 0 deletions. Show diff stats Hide diff stats

  1. 27  verilog/s6ddrphy/patches/s6ddrphy.diff
27  verilog/s6ddrphy/patches/s6ddrphy.diff
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@@ -0,0 +1,27 @@
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+Index: s6ddrphy/spartan6_soft_phy.v
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+===================================================================
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+--- s6ddrphy.orig/spartan6_soft_phy.v
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++++ s6ddrphy/spartan6_soft_phy.v
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+@@ -116,7 +116,6 @@ module spartan6_soft_phy # (
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+     inout  [NUM_DQ-1:0]                         sd_dq,                          // Data in from SDRAM device
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+     output [NUM_DQS-1:0]                        sd_dm,                          // Data mask to SDRAM devices
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+     inout  [NUM_DQS-1:0]                        sd_dqs,                         // DQS
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+-    inout  [NUM_DQS-1:0]                        sd_dqs_n,                       // complimentary DQS
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+ 
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+     // configuration ports
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+     input  [2:0]                                cfg_al,                         // Posted CAS additive latency
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+@@ -300,12 +299,11 @@ genvar j;
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+ generate
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+     for (j = 0; j < NUM_DQ/8*(NIBBLE_DEVICES+1) ; j = j + 1)
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+     begin:dqs_iob
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+-        IOBUFDS iobufds (
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++        IOBUF iobufds (
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+             .O              (sd_dqs_in[j]),
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+             .I              (sd_dqs_out[j]),
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+             .T              (sd_dqs_oe_n[j]),
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+-            .IO             (sd_dqs[j]),
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+-            .IOB            (sd_dqs_n[j])
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++            .IO             (sd_dqs[j])
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+             );
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+     end
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+ endgenerate

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