Skip to content
This repository

HTTPS clone URL

Subversion checkout URL

You can clone with HTTPS or Subversion.

Download ZIP
Browse code

dvisampler: do more deserialization with the ISERDES

  • Loading branch information...
commit d421aae1a55fe2ec489a4159e1b9a466bb6fe7f1 1 parent ffe4bff
Sébastien Bourdeauducq authored September 14, 2013
14  milkymist/dvisampler/clocking.py
@@ -10,7 +10,7 @@ def __init__(self, pads):
10 10
 		self.locked = Signal()
11 11
 		self.serdesstrobe = Signal()
12 12
 		self.clock_domains._cd_pix = ClockDomain()
13  
-		self.clock_domains._cd_pix5x = ClockDomain()
  13
+		self.clock_domains._cd_pix2x = ClockDomain()
14 14
 		self.clock_domains._cd_pix10x = ClockDomain(reset_less=True)
15 15
 
16 16
 		###
@@ -27,7 +27,7 @@ def __init__(self, pads):
27 27
 			p_CLKIN_PERIOD=26.7,
28 28
 			p_CLKFBOUT_MULT=20,
29 29
 			p_CLKOUT0_DIVIDE=2,  # pix10x
30  
-			p_CLKOUT1_DIVIDE=4,  # pix5x
  30
+			p_CLKOUT1_DIVIDE=10, # pix2x
31 31
 			p_CLKOUT2_DIVIDE=20, # pix
32 32
 			p_COMPENSATION="INTERNAL",
33 33
 			
@@ -38,20 +38,20 @@ def __init__(self, pads):
38 38
 
39 39
 		locked_async = Signal()
40 40
 		self.specials += [
41  
-			Instance("BUFPLL", p_DIVIDE=2,
42  
-				i_PLLIN=pll_clk0, i_GCLK=ClockSignal("pix5x"), i_LOCKED=pll_locked,
  41
+			Instance("BUFPLL", p_DIVIDE=5,
  42
+				i_PLLIN=pll_clk0, i_GCLK=ClockSignal("pix2x"), i_LOCKED=pll_locked,
43 43
 				o_IOCLK=self._cd_pix10x.clk, o_LOCK=locked_async, o_SERDESSTROBE=self.serdesstrobe),
44  
-			Instance("BUFG", i_I=pll_clk1, o_O=self._cd_pix5x.clk),
  44
+			Instance("BUFG", i_I=pll_clk1, o_O=self._cd_pix2x.clk),
45 45
 			Instance("BUFG", i_I=pll_clk2, o_O=self._cd_pix.clk),
46 46
 			MultiReg(locked_async, self.locked, "sys")
47 47
 		]
48 48
 		self.comb += self._r_locked.status.eq(self.locked)
49 49
 
50  
-		# sychronize pix+pix5x reset
  50
+		# sychronize pix+pix2x reset
51 51
 		pix_rst_n = 1
52 52
 		for i in range(2):
53 53
 			new_pix_rst_n = Signal()
54 54
 			self.specials += Instance("FDCE", i_D=pix_rst_n, i_CE=1, i_C=ClockSignal("pix"),
55 55
 				i_CLR=~locked_async, o_Q=new_pix_rst_n)
56 56
 			pix_rst_n = new_pix_rst_n
57  
-		self.comb += self._cd_pix.rst.eq(~pix_rst_n), self._cd_pix5x.rst.eq(~pix_rst_n)
  57
+		self.comb += self._cd_pix.rst.eq(~pix_rst_n), self._cd_pix2x.rst.eq(~pix_rst_n)
48  milkymist/dvisampler/datacapture.py
@@ -34,7 +34,7 @@ def __init__(self, pad_p, pad_n, ntbits):
34 34
 			p_COUNTER_WRAPAROUND="STAY_AT_LIMIT", p_DATA_RATE="SDR",
35 35
 
36 36
 			i_IDATAIN=pad_se, o_DATAOUT=pad_delayed_master,
37  
-			i_CLK=ClockSignal("pix5x"), i_IOCLK0=ClockSignal("pix10x"),
  37
+			i_CLK=ClockSignal("pix2x"), i_IOCLK0=ClockSignal("pix10x"),
38 38
 
39 39
 			i_INC=delay_inc, i_CE=delay_ce,
40 40
 			i_CAL=delay_master_cal, i_RST=delay_master_rst, o_BUSY=delay_master_busy,
@@ -42,44 +42,44 @@ def __init__(self, pad_p, pad_n, ntbits):
42 42
 		self.specials += Instance("IODELAY2",
43 43
 			p_SERDES_MODE="SLAVE",
44 44
 			p_DELAY_SRC="IDATAIN", p_IDELAY_TYPE="DIFF_PHASE_DETECTOR",
45  
-			p_COUNTER_WRAPAROUND="STAY_AT_LIMIT", p_DATA_RATE="SDR",
  45
+			p_COUNTER_WRAPAROUND="WRAPAROUND", p_DATA_RATE="SDR",
46 46
 
47 47
 			i_IDATAIN=pad_se, o_DATAOUT=pad_delayed_slave,
48  
-			i_CLK=ClockSignal("pix5x"), i_IOCLK0=ClockSignal("pix10x"),
  48
+			i_CLK=ClockSignal("pix2x"), i_IOCLK0=ClockSignal("pix10x"),
49 49
 
50 50
 			i_INC=delay_inc, i_CE=delay_ce,
51 51
 			i_CAL=delay_slave_cal, i_RST=delay_slave_rst, o_BUSY=delay_slave_busy,
52 52
 			i_T=1)
53 53
 
54  
-		d0 = Signal()
55  
-		d1 = Signal()
  54
+		dsr2 = Signal(5)
56 55
 		pd_valid = Signal()
57 56
 		pd_incdec = Signal()
58 57
 		pd_edge = Signal()
59 58
 		pd_cascade = Signal()
60 59
 		self.specials += Instance("ISERDES2",
61 60
 			p_SERDES_MODE="MASTER",
62  
-			p_BITSLIP_ENABLE="FALSE", p_DATA_RATE="SDR", p_DATA_WIDTH=2,
  61
+			p_BITSLIP_ENABLE="FALSE", p_DATA_RATE="SDR", p_DATA_WIDTH=5,
63 62
 			p_INTERFACE_TYPE="RETIMED",
64 63
 
65 64
 			i_D=pad_delayed_master,
66  
-			o_Q4=d0, o_Q3=d1,
  65
+			o_Q4=dsr2[4], o_Q3=dsr2[3], o_Q2=dsr2[2], o_Q1=dsr2[1],
67 66
 
68 67
 			i_BITSLIP=0, i_CE0=1, i_RST=0,
69  
-			i_CLK0=ClockSignal("pix10x"), i_CLKDIV=ClockSignal("pix5x"),
  68
+			i_CLK0=ClockSignal("pix10x"), i_CLKDIV=ClockSignal("pix2x"),
70 69
 			i_IOCE=self.serdesstrobe,
71 70
 
72 71
 			o_VALID=pd_valid, o_INCDEC=pd_incdec,
73 72
 			i_SHIFTIN=pd_edge, o_SHIFTOUT=pd_cascade)
74 73
 		self.specials += Instance("ISERDES2",
75 74
 			p_SERDES_MODE="SLAVE",
76  
-			p_BITSLIP_ENABLE="FALSE", p_DATA_RATE="SDR", p_DATA_WIDTH=2,
  75
+			p_BITSLIP_ENABLE="FALSE", p_DATA_RATE="SDR", p_DATA_WIDTH=5,
77 76
 			p_INTERFACE_TYPE="RETIMED",
78 77
 
79 78
 			i_D=pad_delayed_slave,
  79
+			o_Q4=dsr2[0],
80 80
 
81 81
 			i_BITSLIP=0, i_CE0=1, i_RST=0,
82  
-			i_CLK0=ClockSignal("pix10x"), i_CLKDIV=ClockSignal("pix5x"),
  82
+			i_CLK0=ClockSignal("pix10x"), i_CLKDIV=ClockSignal("pix2x"),
83 83
 			i_IOCE=self.serdesstrobe,
84 84
 
85 85
 			i_SHIFTIN=pd_cascade, o_SHIFTOUT=pd_edge)
@@ -93,7 +93,7 @@ def __init__(self, pad_p, pad_n, ntbits):
93 93
 			too_late.eq(lateness == (2**ntbits - 1)),
94 94
 			too_early.eq(lateness == 0)
95 95
 		]
96  
-		self.sync.pix5x += [
  96
+		self.sync.pix2x += [
97 97
 			If(reset_lateness,
98 98
 				lateness.eq(2**(ntbits - 1))
99 99
 			).Elif(~delay_master_busy & ~delay_slave_busy & ~too_late & ~too_early,
@@ -103,9 +103,9 @@ def __init__(self, pad_p, pad_n, ntbits):
103 103
 		]
104 104
 
105 105
 		# Delay control
106  
-		self.submodules.delay_master_done = PulseSynchronizer("pix5x", "sys")
  106
+		self.submodules.delay_master_done = PulseSynchronizer("pix2x", "sys")
107 107
 		delay_master_pending = Signal()
108  
-		self.sync.pix5x += [
  108
+		self.sync.pix2x += [
109 109
 			self.delay_master_done.i.eq(0),
110 110
 			If(~delay_master_pending,
111 111
 				If(delay_master_cal | delay_ce, delay_master_pending.eq(1))
@@ -116,9 +116,9 @@ def __init__(self, pad_p, pad_n, ntbits):
116 116
 				)
117 117
 			)
118 118
 		]
119  
-		self.submodules.delay_slave_done = PulseSynchronizer("pix5x", "sys")
  119
+		self.submodules.delay_slave_done = PulseSynchronizer("pix2x", "sys")
120 120
 		delay_slave_pending = Signal()
121  
-		self.sync.pix5x += [
  121
+		self.sync.pix2x += [
122 122
 			self.delay_slave_done.i.eq(0),
123 123
 			If(~delay_slave_pending,
124 124
 				If(delay_slave_cal | delay_ce, delay_slave_pending.eq(1))
@@ -130,12 +130,12 @@ def __init__(self, pad_p, pad_n, ntbits):
130 130
 			)
131 131
 		]
132 132
 
133  
-		self.submodules.do_delay_master_cal = PulseSynchronizer("sys", "pix5x")
134  
-		self.submodules.do_delay_master_rst = PulseSynchronizer("sys", "pix5x")
135  
-		self.submodules.do_delay_slave_cal = PulseSynchronizer("sys", "pix5x")
136  
-		self.submodules.do_delay_slave_rst = PulseSynchronizer("sys", "pix5x")
137  
-		self.submodules.do_delay_inc = PulseSynchronizer("sys", "pix5x")
138  
-		self.submodules.do_delay_dec = PulseSynchronizer("sys", "pix5x")
  133
+		self.submodules.do_delay_master_cal = PulseSynchronizer("sys", "pix2x")
  134
+		self.submodules.do_delay_master_rst = PulseSynchronizer("sys", "pix2x")
  135
+		self.submodules.do_delay_slave_cal = PulseSynchronizer("sys", "pix2x")
  136
+		self.submodules.do_delay_slave_rst = PulseSynchronizer("sys", "pix2x")
  137
+		self.submodules.do_delay_inc = PulseSynchronizer("sys", "pix2x")
  138
+		self.submodules.do_delay_dec = PulseSynchronizer("sys", "pix2x")
139 139
 		self.comb += [
140 140
 			delay_master_cal.eq(self.do_delay_master_cal.o),
141 141
 			delay_master_rst.eq(self.do_delay_master_rst.o),
@@ -174,13 +174,13 @@ def __init__(self, pad_p, pad_n, ntbits):
174 174
 
175 175
 		# Phase detector control
176 176
 		self.specials += MultiReg(Cat(too_late, too_early), self._r_phase.status)
177  
-		self.submodules.do_reset_lateness = PulseSynchronizer("sys", "pix5x")
  177
+		self.submodules.do_reset_lateness = PulseSynchronizer("sys", "pix2x")
178 178
 		self.comb += [
179 179
 			reset_lateness.eq(self.do_reset_lateness.o),
180 180
 			self.do_reset_lateness.i.eq(self._r_phase_reset.re)
181 181
 		]
182 182
 
183  
-		# 2:10 deserialization
  183
+		# 5:10 deserialization
184 184
 		dsr = Signal(10)
185  
-		self.sync.pix5x += dsr.eq(Cat(dsr[2:], d1, d0))
  185
+		self.sync.pix2x += dsr.eq(Cat(dsr[5:], dsr2))
186 186
 		self.sync.pix += self.d.eq(dsr)
4  top.py
@@ -163,8 +163,8 @@ def __init__(self, platform, platform_name, with_memtest):
163 163
 		if platform_name == "mixxeo":
164 164
 			self.submodules.leds = gpio.GPIOOut(platform.request("user_led"))
165 165
 			self.submodules.fb = framebuffer.MixFramebuffer(platform.request("vga"), lasmim_fb0, lasmim_fb1)
166  
-			self.submodules.dvisampler0 = dvisampler.DVISampler(platform.request("dvi_in", 2), lasmim_dvi0)
167  
-			self.submodules.dvisampler1 = dvisampler.DVISampler(platform.request("dvi_in", 3), lasmim_dvi1)
  166
+			self.submodules.dvisampler0 = dvisampler.DVISampler(platform.request("dvi_in", 0), lasmim_dvi0)
  167
+			self.submodules.dvisampler1 = dvisampler.DVISampler(platform.request("dvi_in", 1), lasmim_dvi1)
168 168
 		if platform_name == "m1":
169 169
 			self.submodules.buttons = gpio.GPIOIn(Cat(platform.request("user_btn", 0), platform.request("user_btn", 2)))
170 170
 			self.submodules.leds = gpio.GPIOOut(Cat(*[platform.request("user_led", i) for i in range(2)]))

0 notes on commit d421aae

Please sign in to comment.
Something went wrong with that request. Please try again.