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dvisampler: add HPD registers

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commit dba6189e389a2d563f84efe81dac2ab7efbb8914 1 parent deb438c
Sébastien Bourdeauducq authored September 07, 2013

Showing 1 changed file with 12 additions and 1 deletion. Show diff stats Hide diff stats

  1. 13  milkymist/dvisampler/edid.py
13  milkymist/dvisampler/edid.py
@@ -3,7 +3,7 @@
3 3
 from migen.genlib.cdc import MultiReg
4 4
 from migen.genlib.fsm import FSM, NextState
5 5
 from migen.genlib.misc import chooser
6  
-from migen.bank.description import AutoCSR
  6
+from migen.bank.description import CSRStorage, CSRStatus, AutoCSR
7 7
 
8 8
 _default_edid = [
9 9
 	0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x3D, 0x17, 0x32, 0x12, 0x2A, 0x6A, 0xBF, 0x00,
@@ -18,10 +18,21 @@
18 18
 
19 19
 class EDID(Module, AutoCSR):
20 20
 	def __init__(self, pads, default=_default_edid):
  21
+		self._r_hpd_notif = CSRStatus()
  22
+		self._r_hpd_en = CSRStorage()
21 23
 		self.specials.mem = Memory(8, 128, init=default)
22 24
 
23 25
 		###
24 26
 
  27
+		# HPD
  28
+		if hasattr(pads, "hpd_notif"):
  29
+			self.specials += MultiReg(pads.hpd_notif, self._r_hpd_notif.status)
  30
+		else:
  31
+			self.comb += self._r_hpd_notif.status.eq(1)
  32
+		if hasattr(pads, "hpd_en"):
  33
+			self.comb += pads.hpd_en.eq(self._r_hpd_en.storage)
  34
+
  35
+		# EDID
25 36
 		scl_raw = Signal()
26 37
 		sda_i = Signal()
27 38
 		sda_drv = Signal()

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