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dvisampler: add HPD registers

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commit dba6189e389a2d563f84efe81dac2ab7efbb8914 1 parent deb438c
Sébastien Bourdeauducq sbourdeauducq authored
Showing with 12 additions and 1 deletion.
  1. +12 −1 milkymist/dvisampler/edid.py
13 milkymist/dvisampler/edid.py
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@@ -3,7 +3,7 @@
from migen.genlib.cdc import MultiReg
from migen.genlib.fsm import FSM, NextState
from migen.genlib.misc import chooser
-from migen.bank.description import AutoCSR
+from migen.bank.description import CSRStorage, CSRStatus, AutoCSR
_default_edid = [
0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x3D, 0x17, 0x32, 0x12, 0x2A, 0x6A, 0xBF, 0x00,
@@ -18,10 +18,21 @@
class EDID(Module, AutoCSR):
def __init__(self, pads, default=_default_edid):
+ self._r_hpd_notif = CSRStatus()
+ self._r_hpd_en = CSRStorage()
self.specials.mem = Memory(8, 128, init=default)
###
+ # HPD
+ if hasattr(pads, "hpd_notif"):
+ self.specials += MultiReg(pads.hpd_notif, self._r_hpd_notif.status)
+ else:
+ self.comb += self._r_hpd_notif.status.eq(1)
+ if hasattr(pads, "hpd_en"):
+ self.comb += pads.hpd_en.eq(self._r_hpd_en.storage)
+
+ # EDID
scl_raw = Signal()
sda_i = Signal()
sda_drv = Signal()
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