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Remove uses of the RE signal on field registers

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commit dd6eacba622a8773d53a5910c7dd5f848b1db88b 1 parent c86dd3c
Sébastien Bourdeauducq authored October 09, 2012
9  milkymist/dfii/__init__.py
@@ -15,6 +15,7 @@ def __init__(self, phase):
15 15
 		self._rden = Field("rden", 1, WRITE_ONLY, READ_ONLY)
16 16
 		self._command = RegisterFields("command",
17 17
 			[self._cs, self._we, self._cas, self._ras, self._wren, self._rden])
  18
+		self._command_issue = RegisterRaw("command_issue")
18 19
 		
19 20
 		self._address = RegisterField("address", len(self.phase.address))
20 21
 		self._baddress = RegisterField("baddress", len(self.phase.bank))
@@ -23,13 +24,13 @@ def __init__(self, phase):
23 24
 		self._rddata = RegisterField("rddata", len(self.phase.rddata), READ_ONLY, WRITE_ONLY)
24 25
 	
25 26
 	def get_registers(self):
26  
-		return [self._command,
  27
+		return [self._command, self._command_issue,
27 28
 			self._address, self._baddress,
28 29
 			self._wrdata, self._rddata]
29 30
 		
30 31
 	def get_fragment(self):
31 32
 		comb = [
32  
-			If(self._command.re,
  33
+			If(self._command_issue.re,
33 34
 				self.phase.cs_n.eq(~self._cs.r),
34 35
 				self.phase.we_n.eq(~self._we.r),
35 36
 				self.phase.cas_n.eq(~self._cas.r),
@@ -42,8 +43,8 @@ def get_fragment(self):
42 43
 			),
43 44
 			self.phase.address.eq(self._address.field.r),
44 45
 			self.phase.bank.eq(self._baddress.field.r),
45  
-			self.phase.wrdata_en.eq(self._command.re & self._wren.r),
46  
-			self.phase.rddata_en.eq(self._command.re & self._rden.r),
  46
+			self.phase.wrdata_en.eq(self._command_issue.re & self._wren.r),
  47
+			self.phase.rddata_en.eq(self._command_issue.re & self._rden.r),
47 48
 			self.phase.wrdata.eq(self._wrdata.field.r),
48 49
 			self.phase.wrdata_mask.eq(0)
49 50
 		]
2  milkymist/minimac3/__init__.py
@@ -26,7 +26,7 @@ def __init__(self, address):
26 26
 		self._rx_count_0 = RegisterField("rx_count_0", _count_width, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
27 27
 		self._rx_count_1 = RegisterField("rx_count_1", _count_width, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
28 28
 		self._tx_count = RegisterField("tx_count", _count_width, access_dev=READ_WRITE)
29  
-		self._tx_start = RegisterField("tx_start", access_bus=WRITE_ONLY)
  29
+		self._tx_start = RegisterRaw("tx_start")
30 30
 		regs = [self._phy_reset, self._rx_count_0, self._rx_count_1, self._tx_count, self._tx_start]
31 31
 		
32 32
 		self._rx_event_0 = EventSourcePulse()
32  software/bios/sdram.c
@@ -23,6 +23,18 @@ static void setaddr(int a)
23 23
 	CSR_DFII_AL_P1 = a & 0x00ff;
24 24
 }
25 25
 
  26
+static void command_p0(int cmd)
  27
+{
  28
+	CSR_DFII_COMMAND_P0 = cmd;
  29
+	CSR_DFII_COMMAND_ISSUE_P0 = 1;
  30
+}
  31
+
  32
+static void command_p1(int cmd)
  33
+{
  34
+	CSR_DFII_COMMAND_P1 = cmd;
  35
+	CSR_DFII_COMMAND_ISSUE_P1 = 1;
  36
+}
  37
+
26 38
 static void init_sequence(void)
27 39
 {
28 40
 	int i;
@@ -34,33 +46,33 @@ static void init_sequence(void)
34 46
 	
35 47
 	/* Precharge All */
36 48
 	setaddr(0x0400);
37  
-	CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS;
  49
+	command_p0(DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
38 50
 	
39 51
 	/* Load Extended Mode Register */
40 52
 	CSR_DFII_BA_P0 = 1;
41 53
 	setaddr(0x0000);
42  
-	CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS;
  54
+	command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
43 55
 	CSR_DFII_BA_P0 = 0;
44 56
 	
45 57
 	/* Load Mode Register */
46 58
 	setaddr(0x0132); /* Reset DLL, CL=3, BL=4 */
47  
-	CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS;
  59
+	command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
48 60
 	cdelay(200);
49 61
 	
50 62
 	/* Precharge All */
51 63
 	setaddr(0x0400);
52  
-	CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS;
  64
+	command_p0(DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
53 65
 	
54 66
 	/* 2x Auto Refresh */
55 67
 	for(i=0;i<2;i++) {
56 68
 		setaddr(0);
57  
-		CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_CS;
  69
+		command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_CS);
58 70
 		cdelay(4);
59 71
 	}
60 72
 	
61 73
 	/* Load Mode Register */
62 74
 	setaddr(0x0032); /* CL=3, BL=4 */
63  
-	CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS;
  75
+	command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
64 76
 	cdelay(200);
65 77
 }
66 78
 
@@ -84,7 +96,7 @@ void ddrrow(char *_row)
84 96
 	if(*_row == 0) {
85 97
 		setaddr(0x0000);
86 98
 		CSR_DFII_BA_P0 = 0;
87  
-		CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS;
  99
+		command_p0(DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
88 100
 		cdelay(15);
89 101
 		printf("Precharged\n");
90 102
 	} else {
@@ -95,7 +107,7 @@ void ddrrow(char *_row)
95 107
 		}
96 108
 		setaddr(row);
97 109
 		CSR_DFII_BA_P0 = 0;
98  
-		CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_CS;
  110
+		command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CS);
99 111
 		cdelay(15);
100 112
 		printf("Activated row %d\n", row);
101 113
 	}
@@ -119,7 +131,7 @@ void ddrrd(char *startaddr)
119 131
 	
120 132
 	setaddr(addr);
121 133
 	CSR_DFII_BA_P0 = 0;
122  
-	CSR_DFII_COMMAND_P0 = DFII_COMMAND_CAS|DFII_COMMAND_CS|DFII_COMMAND_RDDATA;
  134
+	command_p0(DFII_COMMAND_CAS|DFII_COMMAND_CS|DFII_COMMAND_RDDATA);
123 135
 	cdelay(15);
124 136
 	
125 137
 	for(i=0;i<8;i++)
@@ -152,7 +164,7 @@ void ddrwr(char *startaddr)
152 164
 	
153 165
 	setaddr(addr);
154 166
 	CSR_DFII_BA_P1 = 0;
155  
-	CSR_DFII_COMMAND_P1 = DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS|DFII_COMMAND_WRDATA;
  167
+	command_p1(DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS|DFII_COMMAND_WRDATA);
156 168
 }
157 169
 
158 170
 #define TEST_SIZE (4*1024*1024)
82  software/include/hw/dfii.h
@@ -12,46 +12,48 @@
12 12
 #define DFII_CONTROL_CKE		0x02
13 13
 
14 14
 #define CSR_DFII_COMMAND_P0		DFII_CSR(0x04)
15  
-#define CSR_DFII_AH_P0			DFII_CSR(0x08)
16  
-#define CSR_DFII_AL_P0			DFII_CSR(0x0C)
17  
-#define CSR_DFII_BA_P0			DFII_CSR(0x10)
18  
-#define CSR_DFII_WD0_P0			DFII_CSR(0x14)
19  
-#define CSR_DFII_WD1_P0			DFII_CSR(0x18)
20  
-#define CSR_DFII_WD2_P0			DFII_CSR(0x1C)
21  
-#define CSR_DFII_WD3_P0			DFII_CSR(0x20)
22  
-#define CSR_DFII_WD4_P0			DFII_CSR(0x24)
23  
-#define CSR_DFII_WD5_P0			DFII_CSR(0x28)
24  
-#define CSR_DFII_WD6_P0			DFII_CSR(0x2C)
25  
-#define CSR_DFII_WD7_P0			DFII_CSR(0x30)
26  
-#define CSR_DFII_RD0_P0			DFII_CSR(0x34)
27  
-#define CSR_DFII_RD1_P0			DFII_CSR(0x38)
28  
-#define CSR_DFII_RD2_P0			DFII_CSR(0x3C)
29  
-#define CSR_DFII_RD3_P0			DFII_CSR(0x40)
30  
-#define CSR_DFII_RD4_P0			DFII_CSR(0x44)
31  
-#define CSR_DFII_RD5_P0			DFII_CSR(0x48)
32  
-#define CSR_DFII_RD6_P0			DFII_CSR(0x4C)
33  
-#define CSR_DFII_RD7_P0			DFII_CSR(0x50)
34  
-
35  
-#define CSR_DFII_COMMAND_P1		DFII_CSR(0x54)
36  
-#define CSR_DFII_AH_P1			DFII_CSR(0x58)
37  
-#define CSR_DFII_AL_P1			DFII_CSR(0x5C)
38  
-#define CSR_DFII_BA_P1			DFII_CSR(0x60)
39  
-#define CSR_DFII_WD0_P1			DFII_CSR(0x64)
40  
-#define CSR_DFII_WD1_P1			DFII_CSR(0x68)
41  
-#define CSR_DFII_WD2_P1			DFII_CSR(0x6C)
42  
-#define CSR_DFII_WD3_P1			DFII_CSR(0x70)
43  
-#define CSR_DFII_WD4_P1			DFII_CSR(0x74)
44  
-#define CSR_DFII_WD5_P1			DFII_CSR(0x78)
45  
-#define CSR_DFII_WD6_P1			DFII_CSR(0x7C)
46  
-#define CSR_DFII_WD7_P1			DFII_CSR(0x80)
47  
-#define CSR_DFII_RD0_P1			DFII_CSR(0x84)
48  
-#define CSR_DFII_RD1_P1			DFII_CSR(0x88)
49  
-#define CSR_DFII_RD2_P1			DFII_CSR(0x8C)
50  
-#define CSR_DFII_RD3_P1			DFII_CSR(0x90)
51  
-#define CSR_DFII_RD4_P1			DFII_CSR(0x94)
52  
-#define CSR_DFII_RD5_P1			DFII_CSR(0x98)
53  
-#define CSR_DFII_RD6_P1			DFII_CSR(0x9C)
54  
-#define CSR_DFII_RD7_P1			DFII_CSR(0xA0)
  15
+#define CSR_DFII_COMMAND_ISSUE_P0	DFII_CSR(0x08)
  16
+#define CSR_DFII_AH_P0			DFII_CSR(0x0C)
  17
+#define CSR_DFII_AL_P0			DFII_CSR(0x10)
  18
+#define CSR_DFII_BA_P0			DFII_CSR(0x14)
  19
+#define CSR_DFII_WD0_P0			DFII_CSR(0x18)
  20
+#define CSR_DFII_WD1_P0			DFII_CSR(0x1C)
  21
+#define CSR_DFII_WD2_P0			DFII_CSR(0x20)
  22
+#define CSR_DFII_WD3_P0			DFII_CSR(0x24)
  23
+#define CSR_DFII_WD4_P0			DFII_CSR(0x28)
  24
+#define CSR_DFII_WD5_P0			DFII_CSR(0x2C)
  25
+#define CSR_DFII_WD6_P0			DFII_CSR(0x30)
  26
+#define CSR_DFII_WD7_P0			DFII_CSR(0x34)
  27
+#define CSR_DFII_RD0_P0			DFII_CSR(0x38)
  28
+#define CSR_DFII_RD1_P0			DFII_CSR(0x3C)
  29
+#define CSR_DFII_RD2_P0			DFII_CSR(0x40)
  30
+#define CSR_DFII_RD3_P0			DFII_CSR(0x44)
  31
+#define CSR_DFII_RD4_P0			DFII_CSR(0x48)
  32
+#define CSR_DFII_RD5_P0			DFII_CSR(0x4C)
  33
+#define CSR_DFII_RD6_P0			DFII_CSR(0x50)
  34
+#define CSR_DFII_RD7_P0			DFII_CSR(0x54)
  35
+
  36
+#define CSR_DFII_COMMAND_P1		DFII_CSR(0x58)
  37
+#define CSR_DFII_COMMAND_ISSUE_P1	DFII_CSR(0x5C)
  38
+#define CSR_DFII_AH_P1			DFII_CSR(0x60)
  39
+#define CSR_DFII_AL_P1			DFII_CSR(0x64)
  40
+#define CSR_DFII_BA_P1			DFII_CSR(0x68)
  41
+#define CSR_DFII_WD0_P1			DFII_CSR(0x6C)
  42
+#define CSR_DFII_WD1_P1			DFII_CSR(0x70)
  43
+#define CSR_DFII_WD2_P1			DFII_CSR(0x74)
  44
+#define CSR_DFII_WD3_P1			DFII_CSR(0x78)
  45
+#define CSR_DFII_WD4_P1			DFII_CSR(0x7C)
  46
+#define CSR_DFII_WD5_P1			DFII_CSR(0x80)
  47
+#define CSR_DFII_WD6_P1			DFII_CSR(0x84)
  48
+#define CSR_DFII_WD7_P1			DFII_CSR(0x88)
  49
+#define CSR_DFII_RD0_P1			DFII_CSR(0x8C)
  50
+#define CSR_DFII_RD1_P1			DFII_CSR(0x90)
  51
+#define CSR_DFII_RD2_P1			DFII_CSR(0x94)
  52
+#define CSR_DFII_RD3_P1			DFII_CSR(0x98)
  53
+#define CSR_DFII_RD4_P1			DFII_CSR(0x9C)
  54
+#define CSR_DFII_RD5_P1			DFII_CSR(0xA0)
  55
+#define CSR_DFII_RD6_P1			DFII_CSR(0xA4)
  56
+#define CSR_DFII_RD7_P1			DFII_CSR(0xA8)
55 57
 
56 58
 #define DFII_COMMAND_CS			0x01
57 59
 #define DFII_COMMAND_WE			0x02

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