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Framebuffer mixing

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commit e96b027deee11ddbeba9d08627922fc5a7662316 1 parent 3ab83fb
Sébastien Bourdeauducq authored May 10, 2013
4  milkymist/dvisampler/debug.py
@@ -41,6 +41,6 @@ def __init__(self, pads, asmiport):
41 41
 			self.packer.sink.stb.eq(fifo.readable),
42 42
 			fifo.re.eq(self.packer.sink.ack),
43 43
 			self.packer.sink.payload.word.eq(fifo.dout),
44  
-			self.packer.source.connect(self.cast.sink, match_by_position=True),
45  
-			self.cast.source.connect(self.dma.data, match_by_position=True)
  44
+			self.packer.source.connect_flat(self.cast.sink),
  45
+			self.cast.source.connect_flat(self.dma.data)
46 46
 		]
76  milkymist/framebuffer/__init__.py
... ...
@@ -1,7 +1,8 @@
1 1
 from migen.fhdl.structure import *
2 2
 from migen.fhdl.module import Module
  3
+from migen.flow.actor import *
3 4
 from migen.flow.network import *
4  
-from migen.bank.description import CSRStorage
  5
+from migen.bank.description import CSRStorage, AutoCSR
5 6
 from migen.actorlib import dma_asmi, structuring, sim, spi
6 7
 
7 8
 from milkymist.framebuffer.lib import bpp, pixel_layout, dac_layout, FrameInitiator, VTG, FIFO
@@ -50,3 +51,76 @@ def __init__(self, pads, asmiport, simulation=False):
50 51
 
51 52
 	def get_csrs(self):
52 53
 		return [self._enable] + self._fi.get_csrs() + self._dma.get_csrs()
  54
+
  55
+class Blender(PipelinedActor, AutoCSR):
  56
+	def __init__(self, nimages, latency):
  57
+		self.sink = Sink([("i"+str(i), pixel_layout) for i in range(nimages)])
  58
+		self.source = Source(pixel_layout)
  59
+		factors = []
  60
+		for i in range(nimages):
  61
+			name = "f"+str(i)
  62
+			csr = CSRStorage(8, name=name)
  63
+			setattr(self, name, csr)
  64
+			factors.append(csr.storage)
  65
+		PipelinedActor.__init__(self, latency)
  66
+
  67
+		###
  68
+
  69
+		imgs = [getattr(self.sink.payload, "i"+str(i)) for i in range(nimages)]
  70
+		outval = Record(pixel_layout)
  71
+		for e in pixel_layout:
  72
+			name = e[0]
  73
+			inpixs = [getattr(img, name) for img in imgs]
  74
+			outpix = getattr(outval, name)
  75
+			for component in ["r", "g", "b"]:
  76
+				incomps = [getattr(pix, component) for pix in inpixs]
  77
+				outcomp = getattr(outpix, component)
  78
+				self.comb += outcomp.eq(sum(incomp*factor for incomp, factor in zip(incomps, factors)) >> 8)
  79
+
  80
+		pipe_stmts = []
  81
+		for i in range(latency):
  82
+			new_outval = Record(pixel_layout)
  83
+			pipe_stmts.append(new_outval.eq(outval))
  84
+			outval = new_outval
  85
+		self.sync += If(self.pipe_ce, pipe_stmts)
  86
+		self.comb += self.source.payload.eq(outval)
  87
+
  88
+class MixFramebuffer(Module, AutoCSR):
  89
+	def __init__(self, pads, *asmiports, blender_latency=3):
  90
+		pack_factor = asmiports[0].hub.dw//(2*bpp)
  91
+		packed_pixels = structuring.pack_layout(pixel_layout, pack_factor)
  92
+		
  93
+		self._enable = CSRStorage()
  94
+		self.fi = FrameInitiator()
  95
+		self.blender = Blender(len(asmiports), blender_latency)
  96
+		self.comb += self.fi.trigger.eq(self._enable.storage)
  97
+
  98
+		g = DataFlowGraph()
  99
+		for n, asmiport in enumerate(asmiports):
  100
+			dma = spi.DMAReadController(dma_asmi.Reader(asmiport), spi.MODE_EXTERNAL, length_reset=640*480*4)
  101
+			cast = structuring.Cast(asmiport.hub.dw, packed_pixels, reverse_to=True)
  102
+			unpack = structuring.Unpack(pack_factor, pixel_layout)
  103
+
  104
+			g.add_connection(dma, cast)
  105
+			g.add_connection(cast, unpack)
  106
+			g.add_connection(unpack, self.blender, sink_subr=["i"+str(n)+"/p0", "i"+str(n)+"/p1"])
  107
+
  108
+			self.comb += dma.generator.trigger.eq(self._enable.storage)
  109
+			setattr(self, "dma"+str(n), dma)
  110
+
  111
+		vtg = VTG()
  112
+		fifo = FIFO()
  113
+		g.add_connection(self.fi, vtg, sink_ep="timing")
  114
+		g.add_connection(self.blender, vtg, sink_ep="pixels")
  115
+		g.add_connection(vtg, fifo)
  116
+		self.submodules += CompositeActor(g)
  117
+		
  118
+		self.comb += [
  119
+			pads.hsync_n.eq(fifo.vga_hsync_n),
  120
+			pads.vsync_n.eq(fifo.vga_vsync_n),
  121
+			pads.r.eq(fifo.vga_r),
  122
+			pads.g.eq(fifo.vga_g),
  123
+			pads.b.eq(fifo.vga_b),
  124
+			pads.psave_n.eq(1)
  125
+		]
  126
+	
4  software/videomixer/Makefile
@@ -32,12 +32,12 @@ main.o: main.c
32 32
 
33 33
 define gen0
34 34
 @echo " GEN " $@
35  
-@sed -e "s/dvisamplerX/dvisampler0/g;s/DVISAMPLERX/DVISAMPLER0/g" $< > $@
  35
+@sed -e "s/dvisamplerX/dvisampler0/g;s/DVISAMPLERX/DVISAMPLER0/g;s/fb_dmaX/fb_dma0/g" $< > $@
36 36
 endef
37 37
 
38 38
 define gen1
39 39
 @echo " GEN " $@
40  
-@sed -e "s/dvisamplerX/dvisampler1/g;s/DVISAMPLERX/DVISAMPLER1/g" $< > $@
  40
+@sed -e "s/dvisamplerX/dvisampler1/g;s/DVISAMPLERX/DVISAMPLER1/g;s/fb_dmaX/fb_dma1/g" $< > $@
41 41
 endef
42 42
 
43 43
 dvisampler0.c: dvisamplerX.c
4  software/videomixer/dvisamplerX.c
@@ -35,7 +35,7 @@ void dvisamplerX_isr(void)
35 35
 	}
36 36
 
37 37
 	if(fb_index != -1)
38  
-		fb_base_write((unsigned int)dvisamplerX_framebuffers[fb_index]);
  38
+		fb_dmaX_base_write((unsigned int)dvisamplerX_framebuffers[fb_index]);
39 39
 }
40 40
 
41 41
 void dvisamplerX_init_video(void)
@@ -57,7 +57,7 @@ void dvisamplerX_init_video(void)
57 57
 	dvisamplerX_dma_slot1_status_write(DVISAMPLER_SLOT_LOADED);
58 58
 	dvisamplerX_next_fb_index = 2;
59 59
 
60  
-	fb_base_write((unsigned int)dvisamplerX_framebuffers[3]);
  60
+	fb_dmaX_base_write((unsigned int)dvisamplerX_framebuffers[3]);
61 61
 }
62 62
 
63 63
 static int dvisamplerX_d0, dvisamplerX_d1, dvisamplerX_d2;
8  software/videomixer/main.c
@@ -21,8 +21,14 @@ int main(void)
21 21
 	timer0_en_write(1);
22 22
 
23 23
 	dvisampler0_init_video();
  24
+	dvisampler1_init_video();
24 25
 	fb_enable_write(1);
25  
-	while(1) dvisampler0_service();
  26
+	fb_blender_f0_write(127);
  27
+	fb_blender_f1_write(127);
  28
+	while(1) {
  29
+		dvisampler0_service();
  30
+		dvisampler1_service();
  31
+	}
26 32
 	
27 33
 	return 0;
28 34
 }
8  top.py
@@ -93,8 +93,10 @@ def __init__(self, platform):
93 93
 		#
94 94
 		self.submodules.asmicon = asmicon.ASMIcon(sdram_phy, sdram_geom, sdram_timing)
95 95
 		asmiport_wb = self.asmicon.hub.get_port()
96  
-		asmiport_fb = self.asmicon.hub.get_port(3)
  96
+		asmiport_fb0 = self.asmicon.hub.get_port(2)
  97
+		asmiport_fb1 = self.asmicon.hub.get_port(2)
97 98
 		asmiport_dvi0 = self.asmicon.hub.get_port(2)
  99
+		asmiport_dvi1 = self.asmicon.hub.get_port(2)
98 100
 		self.asmicon.finalize()
99 101
 		
100 102
 		#
@@ -142,10 +144,10 @@ def __init__(self, platform):
142 144
 		self.submodules.uart = uart.UART(platform.request("serial"), clk_freq, baud=115200)
143 145
 		self.submodules.identifier = identifier.Identifier(0x4D31, version, int(clk_freq))
144 146
 		self.submodules.timer0 = timer.Timer()
145  
-		self.submodules.fb = framebuffer.Framebuffer(platform.request("vga"), asmiport_fb)
  147
+		self.submodules.fb = framebuffer.MixFramebuffer(platform.request("vga"), asmiport_fb0, asmiport_fb1)
146 148
 		self.submodules.asmiprobe = asmiprobe.ASMIprobe(self.asmicon.hub)
147 149
 		self.submodules.dvisampler0 = dvisampler.DVISampler(platform.request("dvi_in", 0), asmiport_dvi0)
148  
-		#self.submodules.dvisampler1 = dvisampler.DVISampler(platform.request("dvi_in", 1))
  150
+		self.submodules.dvisampler1 = dvisampler.DVISampler(platform.request("dvi_in", 1), asmiport_dvi1)
149 151
 
150 152
 		self.submodules.csrbankarray = csrgen.BankArray(self,
151 153
 			lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override])

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