diff --git a/build.py b/build.py
index ef1256785..37dd33763 100755
--- a/build.py
+++ b/build.py
@@ -21,6 +21,8 @@ def main():
 	plat.request("ddram", obj=soc.ddrphy, name_map=lambda s: "sd_" + s)
 	plat.request("eth", obj=soc.minimac, name_map=lambda s: "phy_" + s)
 	plat.request("vga", obj=soc.fb, name_map=lambda s: "vga_" + s)
+	plat.request("dvi_in", 0, obj=soc.dvisampler0)
+	plat.request("dvi_in", 1, obj=soc.dvisampler1)
 	
 	# set extra constraints
 	plat.add_platform_command("""
diff --git a/common/csrbase.h b/common/csrbase.h
index c9f7b1a3c..0b6045a34 100644
--- a/common/csrbase.h
+++ b/common/csrbase.h
@@ -1,12 +1,16 @@
 #ifndef __CSRBASE_H
 #define __CSRBASE_H
 
-#define UART_BASE		0xe0000000
-#define DFII_BASE		0xe0000800
-#define IDENTIFIER_BASE		0xe0001000
-#define TIMER0_BASE		0xe0001800
-#define MINIMAC_BASE		0xe0002000
-#define FB_BASE			0xe0002800
-#define ASMIPROBE_BASE		0xe0003000
+#define UART_BASE			0xe0000000
+#define DFII_BASE			0xe0000800
+#define IDENTIFIER_BASE			0xe0001000
+#define TIMER0_BASE			0xe0001800
+#define MINIMAC_BASE			0xe0002000
+#define FB_BASE				0xe0002800
+#define ASMIPROBE_BASE			0xe0003000
+#define DVISAMPLER0_BASE		0xe0003800
+#define DVISAMPLER0_EDID_MEM_BASE	0xe0004000
+#define DVISAMPLER1_BASE		0xe0004800
+#define DVISAMPLER1_EDID_MEM_BASE	0xe0005000
 
 #endif /* __CSRBASE_H */
diff --git a/top.py b/top.py
index 715183ace..453db3bb7 100644
--- a/top.py
+++ b/top.py
@@ -7,7 +7,7 @@
 from migen.bank import csrgen
 
 from milkymist import m1crg, lm32, norflash, uart, s6ddrphy, dfii, asmicon, \
-	identifier, timer, minimac3, framebuffer, asmiprobe
+	identifier, timer, minimac3, framebuffer, asmiprobe, dvisampler
 from cmacros import get_macros
 
 MHz = 1000000
@@ -119,6 +119,8 @@ def __init__(self):
 		self.submodules.timer0 = timer.Timer()
 		self.submodules.fb = framebuffer.Framebuffer(asmiport_fb)
 		self.submodules.asmiprobe = asmiprobe.ASMIprobe(self.asmicon.hub)
+		self.submodules.dvisampler0 = dvisampler.DVISampler("02")
+		self.submodules.dvisampler1 = dvisampler.DVISampler("02")
 
 		self.submodules.csrbankarray = csrgen.BankArray(self, csr_address_map)
 		self.submodules.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses())