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framebuffer: address generator and DMA

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commit ef13dc1eb1b161d5642b99052521519e3b5fc310 1 parent a52c313
Sébastien Bourdeauducq authored June 17, 2012

Showing 1 changed file with 23 additions and 5 deletions. Show diff stats Hide diff stats

  1. 28  milkymist/framebuffer/__init__.py
28  milkymist/framebuffer/__init__.py
... ...
@@ -1,6 +1,8 @@
1 1
 from migen.fhdl.structure import *
2 2
 from migen.flow.actor import *
3 3
 from migen.flow.network import *
  4
+from migen.flow import ala, plumbing
  5
+from migen.actorlib import control, dma_asmi
4 6
 from migen.bank.description import *
5 7
 from migen.bank import csrgen
6 8
 
@@ -8,9 +10,8 @@
8 10
 _vbits = 11
9 11
 
10 12
 class _FrameInitiator(Actor):
11  
-	def __init__(self, asmi_bits, alignment_bits):
  13
+	def __init__(self, asmi_bits, length_bits, alignment_bits):
12 14
 		self._alignment_bits = alignment_bits
13  
-		length_bits = _hbits + _vbits + 2 - alignment_bits
14 15
 		
15 16
 		self._enable = RegisterField("enable")
16 17
 		
@@ -69,10 +70,25 @@ class Framebuffer:
69 70
 	def __init__(self, address, asmiport):
70 71
 		asmi_bits = asmiport.hub.aw
71 72
 		alignment_bits = asmiport.hub.dw//8
  73
+		length_bits = _hbits + _vbits + 2 - alignment_bits
  74
+		
  75
+		fi = ActorNode(_FrameInitiator(asmi_bits, length_bits, alignment_bits))
  76
+		adrloop = ActorNode(control.For(length_bits))
  77
+		adrbase = ActorNode(ala.Add(BV(asmi_bits)))
  78
+		adrbuffer = ActorNode(plumbing.Buffer)
  79
+		dma = ActorNode(dma_asmi.SequentialReader(asmiport))
  80
+		# TODO: chop
  81
+		# TODO: VTG
72 82
 		
73  
-		fi = _FrameInitiator(asmi_bits, alignment_bits)
  83
+		g = DataFlowGraph()
  84
+		g.add_connection(fi, adrloop, source_subr=["length"])
  85
+		g.add_connection(adrloop, adrbase, sink_subr=["a"])
  86
+		g.add_connection(fi, adrbase, source_subr=["base"], sink_subr=["b"])
  87
+		g.add_connection(adrbase, adrbuffer)
  88
+		g.add_connection(adrbuffer, dma)
  89
+		self._comp_actor = CompositeActor(g)
74 90
 		
75  
-		self.bank = csrgen.Bank(fi.get_registers(), address=address)
  91
+		self.bank = csrgen.Bank(fi.actor.get_registers(), address=address)
76 92
 		
77 93
 		# VGA clock input
78 94
 		self.vga_clk = Signal()
@@ -93,4 +109,6 @@ def get_fragment(self):
93 109
 			self.vga_psave_n.eq(1),
94 110
 			self.vga_blank_n.eq(1)
95 111
 		]
96  
-		return Fragment()
  112
+		return self.bank.get_fragment() \
  113
+			+ self._comp_actor.get_fragment() \
  114
+			+ Fragment(comb)

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