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tb: use default runner

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commit f68fcef90cc90ebfa1c8b8aea6b5831a17841924 1 parent a94ee38
Sébastien Bourdeauducq authored February 09, 2013
3  tb/asmicon/asmicon.py
... ...
@@ -1,7 +1,6 @@
1 1
 from migen.fhdl.structure import *
2 2
 from migen.bus.asmibus import *
3 3
 from migen.sim.generic import Simulator, TopLevel
4  
-from migen.sim.icarus import Runner
5 4
 
6 5
 from milkymist.asmicon import *
7 6
 
@@ -33,7 +32,7 @@ def end_simulation(s):
33 32
 	fragment = dut.get_fragment() + initiator1.get_fragment() + initiator2.get_fragment() + \
34 33
 		logger.get_fragment() + \
35 34
 		Fragment(sim=[end_simulation])
36  
-	sim = Simulator(fragment, Runner(), TopLevel("my.vcd"))
  35
+	sim = Simulator(fragment, TopLevel("my.vcd"))
37 36
 	sim.run(700)
38 37
 
39 38
 main()
3  tb/asmicon/asmicon_wb.py
... ...
@@ -1,7 +1,6 @@
1 1
 from migen.fhdl.structure import *
2 2
 from migen.bus import wishbone, wishbone2asmi, asmibus
3 3
 from migen.sim.generic import Simulator, TopLevel
4  
-from migen.sim.icarus import Runner
5 4
 
6 5
 from milkymist.asmicon import *
7 6
 
@@ -41,7 +40,7 @@ def end_simulation(s):
41 40
 		conn.get_fragment() + \
42 41
 		logger.get_fragment() + \
43 42
 		Fragment(sim=[end_simulation])
44  
-	sim = Simulator(fragment, Runner(), TopLevel("my.vcd"))
  43
+	sim = Simulator(fragment, TopLevel("my.vcd"))
45 44
 	sim.run()
46 45
 
47 46
 main()
3  tb/asmicon/bankmachine.py
... ...
@@ -1,7 +1,6 @@
1 1
 from migen.fhdl.structure import *
2 2
 from migen.bus.asmibus import *
3 3
 from migen.sim.generic import Simulator, TopLevel
4  
-from migen.sim.icarus import Runner
5 4
 
6 5
 from milkymist.asmicon.bankmachine import *
7 6
 
@@ -42,7 +41,7 @@ def end_simulation(s):
42 41
 	fragment = hub.get_fragment() + initiator.get_fragment() + \
43 42
 		dut.get_fragment() + logger.get_fragment() + completer.get_fragment() + \
44 43
 		Fragment(sim=[end_simulation])
45  
-	sim = Simulator(fragment, Runner(), TopLevel("my.vcd"))
  44
+	sim = Simulator(fragment, TopLevel("my.vcd"))
46 45
 	sim.run()
47 46
 
48 47
 main()
3  tb/asmicon/refresher.py
@@ -2,7 +2,6 @@
2 2
 
3 3
 from migen.fhdl.structure import *
4 4
 from migen.sim.generic import Simulator, TopLevel
5  
-from migen.sim.icarus import Runner
6 5
 
7 6
 from milkymist.asmicon.refresher import *
8 7
 
@@ -44,7 +43,7 @@ def main():
44 43
 	logger = CommandLogger(dut.cmd)
45 44
 	granter = Granter(dut.req, dut.ack)
46 45
 	fragment = dut.get_fragment() + logger.get_fragment() + granter.get_fragment()
47  
-	sim = Simulator(fragment, Runner())
  46
+	sim = Simulator(fragment)
48 47
 	sim.run(400)
49 48
 
50 49
 main()
3  tb/asmicon/selector.py
@@ -3,7 +3,6 @@
3 3
 from migen.fhdl.structure import *
4 4
 from migen.bus.asmibus import *
5 5
 from migen.sim.generic import Simulator, TopLevel
6  
-from migen.sim.icarus import Runner
7 6
 
8 7
 from milkymist.asmicon.bankmachine import _AddressSlicer, _SimpleSelector
9 8
 
@@ -71,7 +70,7 @@ def end_simulation(s):
71 70
 	fragment = hub.get_fragment() + sum([i.get_fragment() for i in initiators], Fragment()) + \
72 71
 		logger.get_fragment() + selector.get_fragment() + completer.get_fragment() + \
73 72
 		Fragment(sim=[end_simulation])
74  
-	sim = Simulator(fragment, Runner(), TopLevel("my.vcd"))
  73
+	sim = Simulator(fragment, TopLevel("my.vcd"))
75 74
 	sim.run()
76 75
 
77 76
 main()
3  tb/framebuffer/framebuffer.py
... ...
@@ -1,7 +1,6 @@
1 1
 from migen.fhdl.structure import *
2 2
 from migen.bus import asmibus
3 3
 from migen.sim.generic import Simulator
4  
-from migen.sim.icarus import Runner
5 4
 
6 5
 from milkymist.framebuffer import *
7 6
 
@@ -13,7 +12,7 @@ def main():
13 12
 	dut = Framebuffer(1, port, True)
14 13
 	
15 14
 	fragment = hub.get_fragment() + dut.get_fragment()
16  
-	sim = Simulator(fragment, Runner())
  15
+	sim = Simulator(fragment)
17 16
 	
18 17
 	sim.run(1)
19 18
 	def csr_w(addr, d):

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