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software/videomixer: use new csr.h

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commit f833bc9aa97eee9235a0d0de005bf8a3012d8e3b 1 parent 7a6e564
Sébastien Bourdeauducq authored April 14, 2013
8  software/include/hw/flags.h
@@ -22,4 +22,12 @@
22 22
 #define CLKGEN_STATUS_PROGDONE	0x2
23 23
 #define CLKGEN_STATUS_LOCKED	0x4
24 24
 
  25
+#define DVISAMPLER_TOO_LATE		0x1
  26
+#define DVISAMPLER_TOO_EARLY	0x2
  27
+
  28
+#define DVISAMPLER_DELAY_CAL	0x1
  29
+#define DVISAMPLER_DELAY_RST	0x2
  30
+#define DVISAMPLER_DELAY_INC	0x4
  31
+#define DVISAMPLER_DELAY_DEC	0x8
  32
+
25 33
 #endif /* __HW_FLAGS_H */
3  software/videomixer/isr.c
... ...
@@ -1,5 +1,4 @@
1  
-#include <hw/uart.h>
2  
-#include <interrupt.h>
  1
+#include <hw/csr.h>
3 2
 #include <irq.h>
4 3
 #include <uart.h>
5 4
 
79  software/videomixer/main.c
@@ -3,77 +3,80 @@
3 3
 
4 4
 #include <irq.h>
5 5
 #include <uart.h>
6  
-#include <hw/dvisampler.h>
  6
+#include <hw/csr.h>
  7
+#include <hw/flags.h>
7 8
 
8 9
 static int d0, d1, d2;
9 10
 
10 11
 static void print_status(void)
11 12
 {
12 13
 	printf("Ph: %4d %4d %4d // %d%d%d [%d %d %d] // %d // %dx%d // %d\n", d0, d1, d2,
13  
-		CSR_DVISAMPLER0_D0_CHAR_SYNCED,
14  
-		CSR_DVISAMPLER0_D1_CHAR_SYNCED,
15  
-		CSR_DVISAMPLER0_D2_CHAR_SYNCED,
16  
-		CSR_DVISAMPLER0_D0_CTL_POS,
17  
-		CSR_DVISAMPLER0_D1_CTL_POS,
18  
-		CSR_DVISAMPLER0_D2_CTL_POS,
19  
-		CSR_DVISAMPLER0_CHAN_SYNCED,
20  
-		(CSR_DVISAMPLER0_HRESH << 8) | CSR_DVISAMPLER0_HRESL,
21  
-		(CSR_DVISAMPLER0_VRESH << 8) | CSR_DVISAMPLER0_VRESL,
22  
-		(CSR_DVISAMPLER0_DECNT2 << 16) | (CSR_DVISAMPLER0_DECNT1 << 8) |  CSR_DVISAMPLER0_DECNT0);
  14
+		dvisampler0_data0_charsync_char_synced_read(),
  15
+		dvisampler0_data1_charsync_char_synced_read(),
  16
+		dvisampler0_data2_charsync_char_synced_read(),
  17
+		dvisampler0_data0_charsync_ctl_pos_read(),
  18
+		dvisampler0_data1_charsync_ctl_pos_read(),
  19
+		dvisampler0_data2_charsync_ctl_pos_read(),
  20
+		dvisampler0_chansync_channels_synced_read(),
  21
+		dvisampler0_resdetection_hres_read(),
  22
+		dvisampler0_resdetection_vres_read(),
  23
+		dvisampler0_resdetection_de_cycles_read());
23 24
 }
24 25
 
25 26
 static void calibrate_delays(void)
26 27
 {
27  
-	CSR_DVISAMPLER0_D0_DELAY_CTL = DVISAMPLER_DELAY_CAL;
28  
-	CSR_DVISAMPLER0_D1_DELAY_CTL = DVISAMPLER_DELAY_CAL;
29  
-	CSR_DVISAMPLER0_D2_DELAY_CTL = DVISAMPLER_DELAY_CAL;
30  
-	while(CSR_DVISAMPLER0_D0_DELAY_BUSY || CSR_DVISAMPLER0_D1_DELAY_BUSY || CSR_DVISAMPLER0_D2_DELAY_BUSY);
31  
-	CSR_DVISAMPLER0_D0_DELAY_CTL = DVISAMPLER_DELAY_RST;
32  
-	CSR_DVISAMPLER0_D1_DELAY_CTL = DVISAMPLER_DELAY_RST;
33  
-	CSR_DVISAMPLER0_D2_DELAY_CTL = DVISAMPLER_DELAY_RST;
34  
-	CSR_DVISAMPLER0_D0_PHASE_RESET = 1;
35  
-	CSR_DVISAMPLER0_D1_PHASE_RESET = 1;
36  
-	CSR_DVISAMPLER0_D2_PHASE_RESET = 1;
  28
+	dvisampler0_data0_cap_dly_ctl_write(DVISAMPLER_DELAY_CAL);
  29
+	dvisampler0_data1_cap_dly_ctl_write(DVISAMPLER_DELAY_CAL);
  30
+	dvisampler0_data2_cap_dly_ctl_write(DVISAMPLER_DELAY_CAL);
  31
+	while(dvisampler0_data0_cap_dly_busy_read()
  32
+		|| dvisampler0_data1_cap_dly_busy_read()
  33
+		|| dvisampler0_data2_cap_dly_busy_read());
  34
+	dvisampler0_data0_cap_dly_ctl_write(DVISAMPLER_DELAY_RST);
  35
+	dvisampler0_data1_cap_dly_ctl_write(DVISAMPLER_DELAY_RST);
  36
+	dvisampler0_data2_cap_dly_ctl_write(DVISAMPLER_DELAY_RST);
  37
+	dvisampler0_data0_cap_phase_reset_write(1);
  38
+	dvisampler0_data1_cap_phase_reset_write(1);
  39
+	dvisampler0_data2_cap_phase_reset_write(1);
37 40
 	d0 = d1 = d2 = 0;
38 41
 	printf("Delays calibrated\n");
39 42
 }
40 43
 
41 44
 static void adjust_phase(void)
42 45
 {
43  
-	switch(CSR_DVISAMPLER0_D0_PHASE) {
  46
+	switch(dvisampler0_data0_cap_phase_read()) {
44 47
 		case DVISAMPLER_TOO_LATE:
45  
-			CSR_DVISAMPLER0_D0_DELAY_CTL = DVISAMPLER_DELAY_DEC;
  48
+			dvisampler0_data0_cap_dly_ctl_write(DVISAMPLER_DELAY_DEC);
46 49
 			d0--;
47  
-			CSR_DVISAMPLER0_D0_PHASE_RESET = 1;
  50
+			dvisampler0_data0_cap_phase_reset_write(1);
48 51
 			break;
49 52
 		case DVISAMPLER_TOO_EARLY:
50  
-			CSR_DVISAMPLER0_D0_DELAY_CTL = DVISAMPLER_DELAY_INC;
  53
+			dvisampler0_data0_cap_dly_ctl_write(DVISAMPLER_DELAY_INC);
51 54
 			d0++;
52  
-			CSR_DVISAMPLER0_D0_PHASE_RESET = 1;
  55
+			dvisampler0_data0_cap_phase_reset_write(1);
53 56
 			break;
54 57
 	}
55  
-	switch(CSR_DVISAMPLER0_D1_PHASE) {
  58
+	switch(dvisampler0_data1_cap_phase_read()) {
56 59
 		case DVISAMPLER_TOO_LATE:
57  
-			CSR_DVISAMPLER0_D1_DELAY_CTL = DVISAMPLER_DELAY_DEC;
  60
+			dvisampler0_data1_cap_dly_ctl_write(DVISAMPLER_DELAY_DEC);
58 61
 			d1--;
59  
-			CSR_DVISAMPLER0_D1_PHASE_RESET = 1;
  62
+			dvisampler0_data1_cap_phase_reset_write(1);
60 63
 			break;
61 64
 		case DVISAMPLER_TOO_EARLY:
62  
-			CSR_DVISAMPLER0_D1_DELAY_CTL = DVISAMPLER_DELAY_INC;
  65
+			dvisampler0_data1_cap_dly_ctl_write(DVISAMPLER_DELAY_INC);
63 66
 			d1++;
64  
-			CSR_DVISAMPLER0_D1_PHASE_RESET = 1;
  67
+			dvisampler0_data1_cap_phase_reset_write(1);
65 68
 			break;
66 69
 	}
67  
-	switch(CSR_DVISAMPLER0_D2_PHASE) {
  70
+	switch(dvisampler0_data2_cap_phase_read()) {
68 71
 		case DVISAMPLER_TOO_LATE:
69  
-			CSR_DVISAMPLER0_D2_DELAY_CTL = DVISAMPLER_DELAY_DEC;
  72
+			dvisampler0_data2_cap_dly_ctl_write(DVISAMPLER_DELAY_DEC);
70 73
 			d2--;
71  
-			CSR_DVISAMPLER0_D2_PHASE_RESET = 1;
  74
+			dvisampler0_data2_cap_phase_reset_write(1);
72 75
 			break;
73 76
 		case DVISAMPLER_TOO_EARLY:
74  
-			CSR_DVISAMPLER0_D2_DELAY_CTL = DVISAMPLER_DELAY_INC;
  77
+			dvisampler0_data2_cap_dly_ctl_write(DVISAMPLER_DELAY_INC);
75 78
 			d2++;
76  
-			CSR_DVISAMPLER0_D2_PHASE_RESET = 1;
  79
+			dvisampler0_data2_cap_phase_reset_write(1);
77 80
 			break;
78 81
 	}
79 82
 }
@@ -101,7 +104,7 @@ static void vmix(void)
101 104
 	unsigned int counter;
102 105
 
103 106
 	while(1) {
104  
-		while(!CSR_DVISAMPLER0_PLL_LOCKED);
  107
+		while(!dvisampler0_clocking_locked_read());
105 108
 		printf("PLL locked\n");
106 109
 		calibrate_delays();
107 110
 		if(init_phase())
@@ -111,7 +114,7 @@ static void vmix(void)
111 114
 		print_status();
112 115
 
113 116
 		counter = 0;
114  
-		while(CSR_DVISAMPLER0_PLL_LOCKED) {
  117
+		while(dvisampler0_clocking_locked_read()) {
115 118
 			counter++;
116 119
 			if(counter == 2000000) {
117 120
 				print_status();

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