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dvisampler: use hard differential phase detector

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commit ffe4bff396f74e50317e526ca9459c5ea4c19053 1 parent 8bc1620
Sébastien Bourdeauducq authored September 14, 2013
23  milkymist/dvisampler/__init__.py
@@ -18,27 +18,10 @@ def __init__(self, pads, asmiport, n_dma_slots=2):
18 18
 
19 19
 		for datan in range(3):
20 20
 			name = "data" + str(datan)
21  
-			invert = False
22  
-			if hasattr(pads, name + "_p"):
23  
-				s = Signal()
24  
-				self.specials += Instance("IBUFDS",
25  
-					Instance.Input("I", getattr(pads, name + "_p")),
26  
-					Instance.Input("IB", getattr(pads, name + "_n")),
27  
-					Instance.Output("O", s)		
28  
-				)
29  
-			else:
30  
-				try:
31  
-					s = getattr(pads, name)
32  
-				except AttributeError:
33  
-					s = getattr(pads, name + "_n")
34  
-					invert = True
35 21
 			
36  
-			cap = DataCapture(8, invert)
  22
+			cap = DataCapture(getattr(pads, name + "_p"), getattr(pads, name + "_n"), 8)
37 23
 			setattr(self.submodules, name + "_cap", cap)
38  
-			self.comb += [
39  
-				cap.pad.eq(s),
40  
-				cap.serdesstrobe.eq(self.clocking.serdesstrobe)
41  
-			]
  24
+			self.comb += cap.serdesstrobe.eq(self.clocking.serdesstrobe)
42 25
 
43 26
 			charsync = CharSync()
44 27
 			setattr(self.submodules, name + "_charsync", charsync)
@@ -64,8 +47,6 @@ def __init__(self, pads, asmiport, n_dma_slots=2):
64 47
 			self.chansync.data_in2.eq(self.data2_decod.output),
65 48
 		]
66 49
 
67  
-		###
68  
-
69 50
 		self.submodules.syncpol = SyncPolarity()
70 51
 		self.comb += [
71 52
 			self.syncpol.valid_i.eq(self.chansync.chan_synced),
79  milkymist/dvisampler/clocking.py
@@ -12,77 +12,46 @@ def __init__(self, pads):
12 12
 		self.clock_domains._cd_pix = ClockDomain()
13 13
 		self.clock_domains._cd_pix5x = ClockDomain()
14 14
 		self.clock_domains._cd_pix10x = ClockDomain(reset_less=True)
15  
-		self.clock_domains._cd_pix20x = ClockDomain(reset_less=True)
16 15
 
17 16
 		###
18 17
 
19  
-		if hasattr(pads, "clk_p"):
20  
-			clkin = Signal()
21  
-			self.specials += Instance("IBUFDS",
22  
-				Instance.Input("I", pads.clk_p),
23  
-				Instance.Input("IB", pads.clk_n),
24  
-				Instance.Output("O", clkin)		
25  
-			)
26  
-		else:
27  
-			clkin = pads.clk
  18
+		clk_se = Signal()
  19
+		self.specials += Instance("IBUFDS", i_I=pads.clk_p, i_IB=pads.clk_n, o_O=clk_se)
28 20
 
29 21
 		clkfbout = Signal()
30 22
 		pll_locked = Signal()
31 23
 		pll_clk0 = Signal()
32 24
 		pll_clk1 = Signal()
33 25
 		pll_clk2 = Signal()
34  
-		pll_clk3 = Signal()
35 26
 		self.specials += Instance("PLL_BASE",
36  
-			Instance.Parameter("CLKIN_PERIOD", 26.7),
37  
-			Instance.Parameter("CLKFBOUT_MULT", 20),
38  
-			Instance.Parameter("CLKOUT0_DIVIDE", 1),  # pix20x
39  
-			Instance.Parameter("CLKOUT1_DIVIDE", 4),  # pix5x
40  
-			Instance.Parameter("CLKOUT2_DIVIDE", 20), # pix
41  
-			Instance.Parameter("CLKOUT3_DIVIDE", 2),  # pix10x
42  
-			Instance.Parameter("COMPENSATION", "INTERNAL"),
43  
-
44  
-			Instance.Output("CLKFBOUT", clkfbout),
45  
-			# WARNING: Do not touch the order of those clocks, or PAR fails.
46  
-			Instance.Output("CLKOUT0", pll_clk0),
47  
-			Instance.Output("CLKOUT1", pll_clk1),
48  
-			Instance.Output("CLKOUT2", pll_clk2),
49  
-			Instance.Output("CLKOUT3", pll_clk3),
50  
-			Instance.Output("LOCKED", pll_locked),
51  
-			Instance.Input("CLKFBIN", clkfbout),
52  
-			Instance.Input("CLKIN", clkin),
53  
-			Instance.Input("RST", self._r_pll_reset.storage)
54  
-		)
  27
+			p_CLKIN_PERIOD=26.7,
  28
+			p_CLKFBOUT_MULT=20,
  29
+			p_CLKOUT0_DIVIDE=2,  # pix10x
  30
+			p_CLKOUT1_DIVIDE=4,  # pix5x
  31
+			p_CLKOUT2_DIVIDE=20, # pix
  32
+			p_COMPENSATION="INTERNAL",
  33
+			
  34
+			i_CLKIN=clk_se,
  35
+			o_CLKOUT0=pll_clk0, o_CLKOUT1=pll_clk1, o_CLKOUT2=pll_clk2,
  36
+			o_CLKFBOUT=clkfbout, i_CLKFBIN=clkfbout,
  37
+			o_LOCKED=pll_locked, i_RST=self._r_pll_reset.storage)
55 38
 
56 39
 		locked_async = Signal()
57  
-		self.specials += Instance("BUFPLL",
58  
-			Instance.Parameter("DIVIDE", 4),
59  
-			Instance.Input("PLLIN", pll_clk0),
60  
-			Instance.Input("GCLK", ClockSignal("pix5x")),
61  
-			Instance.Input("LOCKED", pll_locked),
62  
-			Instance.Output("IOCLK", self._cd_pix20x.clk),
63  
-			Instance.Output("LOCK", locked_async),
64  
-			Instance.Output("SERDESSTROBE", self.serdesstrobe)
65  
-		)
66  
-		self.specials += Instance("BUFG",
67  
-			Instance.Input("I", pll_clk1), Instance.Output("O", self._cd_pix5x.clk))
68  
-		self.specials += Instance("BUFG",
69  
-			Instance.Input("I", pll_clk2), Instance.Output("O", self._cd_pix.clk))
70  
-		self.specials += Instance("BUFG",
71  
-			Instance.Input("I", pll_clk3), Instance.Output("O", self._cd_pix10x.clk))
72  
-		self.specials += MultiReg(locked_async, self.locked, "sys")
  40
+		self.specials += [
  41
+			Instance("BUFPLL", p_DIVIDE=2,
  42
+				i_PLLIN=pll_clk0, i_GCLK=ClockSignal("pix5x"), i_LOCKED=pll_locked,
  43
+				o_IOCLK=self._cd_pix10x.clk, o_LOCK=locked_async, o_SERDESSTROBE=self.serdesstrobe),
  44
+			Instance("BUFG", i_I=pll_clk1, o_O=self._cd_pix5x.clk),
  45
+			Instance("BUFG", i_I=pll_clk2, o_O=self._cd_pix.clk),
  46
+			MultiReg(locked_async, self.locked, "sys")
  47
+		]
73 48
 		self.comb += self._r_locked.status.eq(self.locked)
74 49
 
75 50
 		# sychronize pix+pix5x reset
76 51
 		pix_rst_n = 1
77 52
 		for i in range(2):
78 53
 			new_pix_rst_n = Signal()
79  
-			self.specials += Instance("FDCE",
80  
-				Instance.Input("D", pix_rst_n),
81  
-				Instance.Input("CE", 1),
82  
-				Instance.Input("C", ClockSignal("pix")),
83  
-				Instance.Input("CLR", ~locked_async),
84  
-				Instance.Output("Q", new_pix_rst_n)
85  
-			)
  54
+			self.specials += Instance("FDCE", i_D=pix_rst_n, i_CE=1, i_C=ClockSignal("pix"),
  55
+				i_CLR=~locked_async, o_Q=new_pix_rst_n)
86 56
 			pix_rst_n = new_pix_rst_n
87  
-		self.comb += self._cd_pix.rst.eq(~pix_rst_n)
88  
-		self.comb += self._cd_pix5x.rst.eq(~pix_rst_n)
  57
+		self.comb += self._cd_pix.rst.eq(~pix_rst_n), self._cd_pix5x.rst.eq(~pix_rst_n)
210  milkymist/dvisampler/datacapture.py
@@ -3,66 +3,88 @@
3 3
 from migen.bank.description import *
4 4
 
5 5
 class DataCapture(Module, AutoCSR):
6  
-	def __init__(self, ntbits, invert):
7  
-		self.pad = Signal()
  6
+	def __init__(self, pad_p, pad_n, ntbits):
8 7
 		self.serdesstrobe = Signal()
9 8
 		self.d = Signal(10)
10 9
 
11  
-		self._r_dly_ctl = CSR(4)
12  
-		self._r_dly_busy = CSRStatus()
  10
+		self._r_dly_ctl = CSR(6)
  11
+		self._r_dly_busy = CSRStatus(2)
13 12
 		self._r_phase = CSRStatus(2)
14 13
 		self._r_phase_reset = CSR()
15 14
 
16 15
 		###
17 16
 
18 17
 		# IO
19  
-		pad_delayed = Signal()
  18
+		pad_se = Signal()
  19
+		self.specials += Instance("IBUFDS", i_I=pad_p, i_IB=pad_n, o_O=pad_se)
  20
+
  21
+		pad_delayed_master = Signal()
  22
+		pad_delayed_slave = Signal()
20 23
 		delay_inc = Signal()
21 24
 		delay_ce = Signal()
22  
-		delay_cal = Signal()
23  
-		delay_rst = Signal()
24  
-		delay_busy = Signal()
  25
+		delay_master_cal = Signal()
  26
+		delay_master_rst = Signal()
  27
+		delay_master_busy = Signal()
  28
+		delay_slave_cal = Signal()
  29
+		delay_slave_rst = Signal()
  30
+		delay_slave_busy = Signal()
  31
+		self.specials += Instance("IODELAY2",
  32
+			p_SERDES_MODE="MASTER",
  33
+			p_DELAY_SRC="IDATAIN", p_IDELAY_TYPE="DIFF_PHASE_DETECTOR",
  34
+			p_COUNTER_WRAPAROUND="STAY_AT_LIMIT", p_DATA_RATE="SDR",
  35
+
  36
+			i_IDATAIN=pad_se, o_DATAOUT=pad_delayed_master,
  37
+			i_CLK=ClockSignal("pix5x"), i_IOCLK0=ClockSignal("pix10x"),
  38
+
  39
+			i_INC=delay_inc, i_CE=delay_ce,
  40
+			i_CAL=delay_master_cal, i_RST=delay_master_rst, o_BUSY=delay_master_busy,
  41
+			i_T=1)
25 42
 		self.specials += Instance("IODELAY2",
26  
-			Instance.Parameter("DELAY_SRC", "IDATAIN"),
27  
-			Instance.Parameter("IDELAY_TYPE", "VARIABLE_FROM_HALF_MAX"),
28  
-			Instance.Parameter("COUNTER_WRAPAROUND", "STAY_AT_LIMIT"),
29  
-			Instance.Parameter("DATA_RATE", "SDR"),
30  
-			Instance.Input("IDATAIN", self.pad),
31  
-			Instance.Output("DATAOUT", pad_delayed),
32  
-			Instance.Input("CLK", ClockSignal("pix5x")),
33  
-			Instance.Input("IOCLK0", ClockSignal("pix10x")),
34  
-			Instance.Input("INC", delay_inc),
35  
-			Instance.Input("CE", delay_ce),
36  
-			Instance.Input("CAL", delay_cal),
37  
-			Instance.Input("RST", delay_rst),
38  
-			Instance.Output("BUSY", delay_busy),
39  
-			Instance.Input("T", 1)
40  
-		)
  43
+			p_SERDES_MODE="SLAVE",
  44
+			p_DELAY_SRC="IDATAIN", p_IDELAY_TYPE="DIFF_PHASE_DETECTOR",
  45
+			p_COUNTER_WRAPAROUND="STAY_AT_LIMIT", p_DATA_RATE="SDR",
  46
+
  47
+			i_IDATAIN=pad_se, o_DATAOUT=pad_delayed_slave,
  48
+			i_CLK=ClockSignal("pix5x"), i_IOCLK0=ClockSignal("pix10x"),
  49
+
  50
+			i_INC=delay_inc, i_CE=delay_ce,
  51
+			i_CAL=delay_slave_cal, i_RST=delay_slave_rst, o_BUSY=delay_slave_busy,
  52
+			i_T=1)
41 53
 
42 54
 		d0 = Signal()
43  
-		d0p = Signal()
44 55
 		d1 = Signal()
45  
-		d1p = Signal()
  56
+		pd_valid = Signal()
  57
+		pd_incdec = Signal()
  58
+		pd_edge = Signal()
  59
+		pd_cascade = Signal()
46 60
 		self.specials += Instance("ISERDES2",
47  
-			Instance.Parameter("BITSLIP_ENABLE", "FALSE"),
48  
-			Instance.Parameter("DATA_RATE", "SDR"),
49  
-			Instance.Parameter("DATA_WIDTH", 4),
50  
-			Instance.Parameter("INTERFACE_TYPE", "RETIMED"),
51  
-			Instance.Parameter("SERDES_MODE", "NONE"),
52  
-			Instance.Output("Q4", d0),
53  
-			Instance.Output("Q3", d0p),
54  
-			Instance.Output("Q2", d1),
55  
-			Instance.Output("Q1", d1p),
56  
-			Instance.Input("BITSLIP", 0),
57  
-			Instance.Input("CE0", 1),
58  
-			Instance.Input("CLK0", ClockSignal("pix20x")),
59  
-			Instance.Input("CLKDIV", ClockSignal("pix5x")),
60  
-			Instance.Input("D", pad_delayed),
61  
-			Instance.Input("IOCE", self.serdesstrobe),
62  
-			Instance.Input("RST", 0)
63  
-		)
64  
-
65  
-		# Phase detector
  61
+			p_SERDES_MODE="MASTER",
  62
+			p_BITSLIP_ENABLE="FALSE", p_DATA_RATE="SDR", p_DATA_WIDTH=2,
  63
+			p_INTERFACE_TYPE="RETIMED",
  64
+
  65
+			i_D=pad_delayed_master,
  66
+			o_Q4=d0, o_Q3=d1,
  67
+
  68
+			i_BITSLIP=0, i_CE0=1, i_RST=0,
  69
+			i_CLK0=ClockSignal("pix10x"), i_CLKDIV=ClockSignal("pix5x"),
  70
+			i_IOCE=self.serdesstrobe,
  71
+
  72
+			o_VALID=pd_valid, o_INCDEC=pd_incdec,
  73
+			i_SHIFTIN=pd_edge, o_SHIFTOUT=pd_cascade)
  74
+		self.specials += Instance("ISERDES2",
  75
+			p_SERDES_MODE="SLAVE",
  76
+			p_BITSLIP_ENABLE="FALSE", p_DATA_RATE="SDR", p_DATA_WIDTH=2,
  77
+			p_INTERFACE_TYPE="RETIMED",
  78
+
  79
+			i_D=pad_delayed_slave,
  80
+
  81
+			i_BITSLIP=0, i_CE0=1, i_RST=0,
  82
+			i_CLK0=ClockSignal("pix10x"), i_CLKDIV=ClockSignal("pix5x"),
  83
+			i_IOCE=self.serdesstrobe,
  84
+
  85
+			i_SHIFTIN=pd_cascade, o_SHIFTOUT=pd_edge)
  86
+
  87
+		# Phase error accumulator
66 88
 		lateness = Signal(ntbits, reset=2**(ntbits - 1))
67 89
 		too_late = Signal()
68 90
 		too_early = Signal()
@@ -74,68 +96,80 @@ def __init__(self, ntbits, invert):
74 96
 		self.sync.pix5x += [
75 97
 			If(reset_lateness,
76 98
 				lateness.eq(2**(ntbits - 1))
77  
-			).Elif(~delay_busy & ~too_late & ~too_early & (d0 != d1),
78  
-				If(d0,
79  
-					# 1 -----> 0
80  
-					#    d0p
81  
-					If(d0p,
82  
-						lateness.eq(lateness - 1)
83  
-					).Else(
84  
-						lateness.eq(lateness + 1)
85  
-					)
86  
-				).Else(
87  
-					# 0 -----> 1
88  
-					#    d0p
89  
-					If(d0p,
90  
-						lateness.eq(lateness + 1)
91  
-					).Else(
92  
-						lateness.eq(lateness - 1)
93  
-					)
94  
-				)
  99
+			).Elif(~delay_master_busy & ~delay_slave_busy & ~too_late & ~too_early,
  100
+				If(pd_valid &  pd_incdec, lateness.eq(lateness - 1)),
  101
+				If(pd_valid & ~pd_incdec, lateness.eq(lateness + 1))
95 102
 			)
96 103
 		]
97 104
 
98 105
 		# Delay control
99  
-		self.submodules.delay_done = PulseSynchronizer("pix5x", "sys")
100  
-		delay_pending = Signal()
  106
+		self.submodules.delay_master_done = PulseSynchronizer("pix5x", "sys")
  107
+		delay_master_pending = Signal()
  108
+		self.sync.pix5x += [
  109
+			self.delay_master_done.i.eq(0),
  110
+			If(~delay_master_pending,
  111
+				If(delay_master_cal | delay_ce, delay_master_pending.eq(1))
  112
+			).Else(
  113
+				If(~delay_master_busy,
  114
+					self.delay_master_done.i.eq(1),
  115
+					delay_master_pending.eq(0)
  116
+				)
  117
+			)
  118
+		]
  119
+		self.submodules.delay_slave_done = PulseSynchronizer("pix5x", "sys")
  120
+		delay_slave_pending = Signal()
101 121
 		self.sync.pix5x += [
102  
-			self.delay_done.i.eq(0),
103  
-			If(~delay_pending,
104  
-				If(delay_cal | delay_ce, delay_pending.eq(1))
  122
+			self.delay_slave_done.i.eq(0),
  123
+			If(~delay_slave_pending,
  124
+				If(delay_slave_cal | delay_ce, delay_slave_pending.eq(1))
105 125
 			).Else(
106  
-				If(~delay_busy,
107  
-					self.delay_done.i.eq(1),
108  
-					delay_pending.eq(0)
  126
+				If(~delay_slave_busy,
  127
+					self.delay_slave_done.i.eq(1),
  128
+					delay_slave_pending.eq(0)
109 129
 				)
110 130
 			)
111 131
 		]
112 132
 
113  
-		self.submodules.do_delay_cal = PulseSynchronizer("sys", "pix5x")
114  
-		self.submodules.do_delay_rst = PulseSynchronizer("sys", "pix5x")
  133
+		self.submodules.do_delay_master_cal = PulseSynchronizer("sys", "pix5x")
  134
+		self.submodules.do_delay_master_rst = PulseSynchronizer("sys", "pix5x")
  135
+		self.submodules.do_delay_slave_cal = PulseSynchronizer("sys", "pix5x")
  136
+		self.submodules.do_delay_slave_rst = PulseSynchronizer("sys", "pix5x")
115 137
 		self.submodules.do_delay_inc = PulseSynchronizer("sys", "pix5x")
116 138
 		self.submodules.do_delay_dec = PulseSynchronizer("sys", "pix5x")
117 139
 		self.comb += [
118  
-			delay_cal.eq(self.do_delay_cal.o),
119  
-			delay_rst.eq(self.do_delay_rst.o),
  140
+			delay_master_cal.eq(self.do_delay_master_cal.o),
  141
+			delay_master_rst.eq(self.do_delay_master_rst.o),
  142
+			delay_slave_cal.eq(self.do_delay_slave_cal.o),
  143
+			delay_slave_rst.eq(self.do_delay_slave_rst.o),
120 144
 			delay_inc.eq(self.do_delay_inc.o),
121 145
 			delay_ce.eq(self.do_delay_inc.o | self.do_delay_dec.o),
122 146
 		]
123 147
 
124  
-		sys_delay_pending = Signal()
  148
+		sys_delay_master_pending = Signal()
  149
+		self.sync += [
  150
+			If(self.do_delay_master_cal.i | self.do_delay_inc.i | self.do_delay_dec.i,
  151
+				sys_delay_master_pending.eq(1)
  152
+			).Elif(self.delay_master_done.o,
  153
+				sys_delay_master_pending.eq(0)
  154
+			)
  155
+		]
  156
+		sys_delay_slave_pending = Signal()
125 157
 		self.sync += [
126  
-			If(self.do_delay_cal.i | self.do_delay_inc.i | self.do_delay_dec.i,
127  
-				sys_delay_pending.eq(1)
128  
-			).Elif(self.delay_done.o,
129  
-				sys_delay_pending.eq(0)
  158
+			If(self.do_delay_slave_cal.i | self.do_delay_inc.i | self.do_delay_dec.i,
  159
+				sys_delay_slave_pending.eq(1)
  160
+			).Elif(self.delay_slave_done.o,
  161
+				sys_delay_slave_pending.eq(0)
130 162
 			)
131 163
 		]
132 164
 
133 165
 		self.comb += [
134  
-			self.do_delay_cal.i.eq(self._r_dly_ctl.re & self._r_dly_ctl.r[0]),
135  
-			self.do_delay_rst.i.eq(self._r_dly_ctl.re & self._r_dly_ctl.r[1]),
136  
-			self.do_delay_inc.i.eq(self._r_dly_ctl.re & self._r_dly_ctl.r[2]),
137  
-			self.do_delay_dec.i.eq(self._r_dly_ctl.re & self._r_dly_ctl.r[3]),
138  
-			self._r_dly_busy.status.eq(sys_delay_pending)
  166
+			self.do_delay_master_cal.i.eq(self._r_dly_ctl.re & self._r_dly_ctl.r[0]),
  167
+			self.do_delay_master_rst.i.eq(self._r_dly_ctl.re & self._r_dly_ctl.r[1]),
  168
+			self.do_delay_slave_cal.i.eq(self._r_dly_ctl.re & self._r_dly_ctl.r[2]),
  169
+			self.do_delay_slave_rst.i.eq(self._r_dly_ctl.re & self._r_dly_ctl.r[3]),
  170
+			self.do_delay_inc.i.eq(self._r_dly_ctl.re & self._r_dly_ctl.r[4]),
  171
+			self.do_delay_dec.i.eq(self._r_dly_ctl.re & self._r_dly_ctl.r[5]),
  172
+			self._r_dly_busy.status.eq(Cat(sys_delay_master_pending, sys_delay_slave_pending))
139 173
 		]
140 174
 
141 175
 		# Phase detector control
@@ -147,12 +181,6 @@ def __init__(self, ntbits, invert):
147 181
 		]
148 182
 
149 183
 		# 2:10 deserialization
150  
-		d0i = Signal()
151  
-		d1i = Signal()
152  
-		self.comb += [
153  
-			d0i.eq(d0 ^ invert),
154  
-			d1i.eq(d1 ^ invert)
155  
-		]
156 184
 		dsr = Signal(10)
157  
-		self.sync.pix5x += dsr.eq(Cat(dsr[2:], d1i, d0i))
  185
+		self.sync.pix5x += dsr.eq(Cat(dsr[2:], d1, d0))
158 186
 		self.sync.pix += self.d.eq(dsr)
10  software/include/hw/flags.h
@@ -25,10 +25,12 @@
25 25
 #define DVISAMPLER_TOO_LATE		0x1
26 26
 #define DVISAMPLER_TOO_EARLY	0x2
27 27
 
28  
-#define DVISAMPLER_DELAY_CAL	0x1
29  
-#define DVISAMPLER_DELAY_RST	0x2
30  
-#define DVISAMPLER_DELAY_INC	0x4
31  
-#define DVISAMPLER_DELAY_DEC	0x8
  28
+#define DVISAMPLER_DELAY_MASTER_CAL	0x01
  29
+#define DVISAMPLER_DELAY_MASTER_RST	0x02
  30
+#define DVISAMPLER_DELAY_SLAVE_CAL	0x04
  31
+#define DVISAMPLER_DELAY_SLAVE_RST	0x08
  32
+#define DVISAMPLER_DELAY_INC		0x10
  33
+#define DVISAMPLER_DELAY_DEC		0x20
32 34
 
33 35
 #define DVISAMPLER_SLOT_EMPTY	0
34 36
 #define DVISAMPLER_SLOT_LOADED	1
12  software/videomixer/dvisamplerX.c
@@ -106,14 +106,14 @@ static int wait_idelays(void)
106 106
 
107 107
 int dvisamplerX_calibrate_delays(void)
108 108
 {
109  
-	dvisamplerX_data0_cap_dly_ctl_write(DVISAMPLER_DELAY_CAL);
110  
-	dvisamplerX_data1_cap_dly_ctl_write(DVISAMPLER_DELAY_CAL);
111  
-	dvisamplerX_data2_cap_dly_ctl_write(DVISAMPLER_DELAY_CAL);
  109
+	dvisamplerX_data0_cap_dly_ctl_write(DVISAMPLER_DELAY_MASTER_CAL|DVISAMPLER_DELAY_SLAVE_CAL);
  110
+	dvisamplerX_data1_cap_dly_ctl_write(DVISAMPLER_DELAY_MASTER_CAL|DVISAMPLER_DELAY_SLAVE_CAL);
  111
+	dvisamplerX_data2_cap_dly_ctl_write(DVISAMPLER_DELAY_MASTER_CAL|DVISAMPLER_DELAY_SLAVE_CAL);
112 112
 	if(!wait_idelays())
113 113
 		return 0;
114  
-	dvisamplerX_data0_cap_dly_ctl_write(DVISAMPLER_DELAY_RST);
115  
-	dvisamplerX_data1_cap_dly_ctl_write(DVISAMPLER_DELAY_RST);
116  
-	dvisamplerX_data2_cap_dly_ctl_write(DVISAMPLER_DELAY_RST);
  114
+	dvisamplerX_data0_cap_dly_ctl_write(DVISAMPLER_DELAY_MASTER_RST|DVISAMPLER_DELAY_SLAVE_RST);
  115
+	dvisamplerX_data1_cap_dly_ctl_write(DVISAMPLER_DELAY_MASTER_RST|DVISAMPLER_DELAY_SLAVE_RST);
  116
+	dvisamplerX_data2_cap_dly_ctl_write(DVISAMPLER_DELAY_MASTER_RST|DVISAMPLER_DELAY_SLAVE_RST);
117 117
 	dvisamplerX_data0_cap_phase_reset_write(1);
118 118
 	dvisamplerX_data1_cap_phase_reset_write(1);
119 119
 	dvisamplerX_data2_cap_phase_reset_write(1);

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