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  • 2 commits
  • 4 files changed
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  • 1 contributor
2  milkymist/asmicon/bankmachine.py
@@ -31,7 +31,7 @@ def col(self, address):
31 31
 		if isinstance(address, int):
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 			return (address & (2**self._b1 - 1)) << self.address_align
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 		else:
34  
-			return Cat(Constant(0, BV(self.address_align)), address[:self._b1])
  34
+			return Cat(Replicate(0, self.address_align), address[:self._b1])
35 35
 
36 36
 class _Selector:
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 	def __init__(self, slicer, bankn, slots):
5  milkymist/asmicon/multiplexer.py
@@ -71,7 +71,7 @@ def get_fragment(self):
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 		sync = []
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 		def stb_and(cmd, attr):
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 			if not hasattr(cmd, "stb"):
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-				return Constant(0)
  74
+				return 0
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 			else:
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 				return cmd.stb & getattr(cmd, attr)
77 77
 		for phase, sel in zip(self.dfi.phases, self.sel):
@@ -251,9 +251,10 @@ def anti_starvation(timeout):
251 251
 		)
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 		fsm.act(fsm.REFRESH,
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 			steerer.sel[0].eq(STEER_REFRESH),
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-			self.refresher.ack.eq(1),
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 			If(~self.refresher.req, fsm.next_state(fsm.READ))
256 255
 		)
  256
+		# FIXME: workaround for zero-delay loop simulation problem with Icarus Verilog
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+		comb.append(self.refresher.ack.eq(fsm._state == fsm.REFRESH))
257 258
 		
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 		return Fragment(comb, sync) + \
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 			choose_cmd.get_fragment() + \
4  milkymist/uart/__init__.py
@@ -21,7 +21,7 @@ def get_fragment(self):
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 		enable16 = Signal()
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 		enable16_counter = Signal(BV(16))
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 		comb = [
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-			enable16.eq(enable16_counter == Constant(0, BV(16)))
  24
+			enable16.eq(enable16_counter == 0)
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 		]
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 		sync = [
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 			enable16_counter.eq(enable16_counter - 1),
@@ -43,7 +43,7 @@ def get_fragment(self):
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 				self.tx.eq(0)
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 			).Elif(enable16 & tx_busy,
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 				tx_count16.eq(tx_count16 + 1),
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-				If(tx_count16 == Constant(0, BV(4)),
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+				If(tx_count16 == 0,
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 					tx_bitcount.eq(tx_bitcount + 1),
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 					If(tx_bitcount == 8,
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 						self.tx.eq(1)
13  top.py
@@ -97,14 +97,13 @@ def get():
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 			cpu0.ibus,
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 			cpu0.dbus
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 		], [
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-			(binc("000"), norflash0.bus),
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-			(binc("001"), sram0.bus),
102  
-			(binc("011"), minimac0.membus),
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-			(binc("10"), wishbone2asmi0.wishbone),
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-			(binc("11"), wishbone2csr0.wishbone)
  100
+			(lambda a: a[26:29] == 0, norflash0.bus),
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+			(lambda a: a[26:29] == 1, sram0.bus),
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+			(lambda a: a[26:29] == 3, minimac0.membus),
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+			(lambda a: a[27:29] == 2, wishbone2asmi0.wishbone),
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+			(lambda a: a[27:29] == 3, wishbone2csr0.wishbone)
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 		],
106  
-		register=True,
107  
-		offset=1)
  106
+		register=True)
108 107
 	
109 108
 	#
110 109
 	# CSR

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