Skip to content

HTTPS clone URL

Subversion checkout URL

You can clone with
or
.
Download ZIP
  • 2 commits
  • 4 files changed
  • 0 commit comments
  • 1 contributor
View
2  milkymist/asmicon/bankmachine.py
@@ -31,7 +31,7 @@ def col(self, address):
if isinstance(address, int):
return (address & (2**self._b1 - 1)) << self.address_align
else:
- return Cat(Constant(0, BV(self.address_align)), address[:self._b1])
+ return Cat(Replicate(0, self.address_align), address[:self._b1])
class _Selector:
def __init__(self, slicer, bankn, slots):
View
5 milkymist/asmicon/multiplexer.py
@@ -71,7 +71,7 @@ def get_fragment(self):
sync = []
def stb_and(cmd, attr):
if not hasattr(cmd, "stb"):
- return Constant(0)
+ return 0
else:
return cmd.stb & getattr(cmd, attr)
for phase, sel in zip(self.dfi.phases, self.sel):
@@ -251,9 +251,10 @@ def anti_starvation(timeout):
)
fsm.act(fsm.REFRESH,
steerer.sel[0].eq(STEER_REFRESH),
- self.refresher.ack.eq(1),
If(~self.refresher.req, fsm.next_state(fsm.READ))
)
+ # FIXME: workaround for zero-delay loop simulation problem with Icarus Verilog
+ comb.append(self.refresher.ack.eq(fsm._state == fsm.REFRESH))
return Fragment(comb, sync) + \
choose_cmd.get_fragment() + \
View
4 milkymist/uart/__init__.py
@@ -21,7 +21,7 @@ def get_fragment(self):
enable16 = Signal()
enable16_counter = Signal(BV(16))
comb = [
- enable16.eq(enable16_counter == Constant(0, BV(16)))
+ enable16.eq(enable16_counter == 0)
]
sync = [
enable16_counter.eq(enable16_counter - 1),
@@ -43,7 +43,7 @@ def get_fragment(self):
self.tx.eq(0)
).Elif(enable16 & tx_busy,
tx_count16.eq(tx_count16 + 1),
- If(tx_count16 == Constant(0, BV(4)),
+ If(tx_count16 == 0,
tx_bitcount.eq(tx_bitcount + 1),
If(tx_bitcount == 8,
self.tx.eq(1)
View
13 top.py
@@ -97,14 +97,13 @@ def get():
cpu0.ibus,
cpu0.dbus
], [
- (binc("000"), norflash0.bus),
- (binc("001"), sram0.bus),
- (binc("011"), minimac0.membus),
- (binc("10"), wishbone2asmi0.wishbone),
- (binc("11"), wishbone2csr0.wishbone)
+ (lambda a: a[26:29] == 0, norflash0.bus),
+ (lambda a: a[26:29] == 1, sram0.bus),
+ (lambda a: a[26:29] == 3, minimac0.membus),
+ (lambda a: a[27:29] == 2, wishbone2asmi0.wishbone),
+ (lambda a: a[27:29] == 3, wishbone2csr0.wishbone)
],
- register=True,
- offset=1)
+ register=True)
#
# CSR

No commit comments for this range

Something went wrong with that request. Please try again.