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6  build.py
@@ -27,10 +27,6 @@ def main():
27 27
 TIMESPEC "TSphy_tx_clk_io" = FROM "GRPphy_tx_clk" TO "PADS" 10 ns;
28 28
 TIMESPEC "TSphy_rx_clk_io" = FROM "PADS" TO "GRPphy_rx_clk" 10 ns;
29 29
 
30  
-NET "asfifo*/counter_read/gray_count*" TIG;
31  
-NET "asfifo*/counter_write/gray_count*" TIG;
32  
-NET "asfifo*/preset_empty*" TIG;
33  
-
34 30
 NET "{dviclk0}" TNM_NET = "GRPdviclk0";
35 31
 NET "{dviclk0}" CLOCK_DEDICATED_ROUTE = FALSE;
36 32
 TIMESPEC "TSdviclk0" = PERIOD "GRPdviclk0" 26.7 ns HIGH 50%;
@@ -44,7 +40,7 @@ def main():
44 40
 		dviclk0=platform.lookup_request("dvi_in", 0).clk,
45 41
 		dviclk1=platform.lookup_request("dvi_in", 1).clk)
46 42
 	
47  
-	for d in ["generic", "m1crg", "s6ddrphy", "minimac3"]:
  43
+	for d in ["m1crg", "s6ddrphy", "minimac3"]:
48 44
 		platform.add_source_dir(os.path.join("verilog", d))
49 45
 	platform.add_sources(os.path.join("verilog", "lm32", "submodule", "rtl"), 
50 46
 		"lm32_cpu.v", "lm32_instruction_unit.v", "lm32_decoder.v",
33  milkymist/framebuffer/__init__.py
@@ -2,6 +2,7 @@
2 2
 from migen.fhdl.specials import Instance
3 3
 from migen.fhdl.module import Module
4 4
 from migen.genlib.record import Record
  5
+from migen.genlib.fifo import AsyncFIFO
5 6
 from migen.flow.actor import *
6 7
 from migen.flow.network import *
7 8
 from migen.flow.transactions import *
@@ -132,33 +133,15 @@ def __init__(self):
132 133
 		###
133 134
 
134 135
 		data_width = 2+2*3*_bpc_dac
135  
-		fifo_full = Signal()
136  
-		fifo_write_en = Signal()
137  
-		fifo_read_en = Signal()
138  
-		fifo_data_out = Signal(data_width)
139  
-		fifo_data_in = Signal(data_width)
140  
-		self.specials += Instance("asfifo",
141  
-			Instance.Parameter("data_width", data_width),
142  
-			Instance.Parameter("address_width", 8),
143  
-	
144  
-			Instance.Output("data_out", fifo_data_out),
145  
-			Instance.Output("empty"),
146  
-			Instance.Input("read_en", fifo_read_en),
147  
-			Instance.Input("clk_read", ClockSignal("vga")),
148  
-
149  
-			Instance.Input("data_in", fifo_data_in),
150  
-			Instance.Output("full", fifo_full),
151  
-			Instance.Input("write_en", fifo_write_en),
152  
-			Instance.Input("clk_write", ClockSignal()),
153  
-			
154  
-			Instance.Input("rst", 0))
  136
+		fifo = AsyncFIFO(data_width, 256)
  137
+		self.add_submodule(fifo, {"write": "sys", "read": "vga"})
155 138
 		fifo_in = self.dac.payload
156 139
 		fifo_out = Record(_dac_layout)
157 140
 		self.comb += [
158  
-			self.dac.ack.eq(~fifo_full),
159  
-			fifo_write_en.eq(self.dac.stb),
160  
-			fifo_data_in.eq(fifo_in.raw_bits()),
161  
-			fifo_out.raw_bits().eq(fifo_data_out),
  141
+			self.dac.ack.eq(fifo.writable),
  142
+			fifo.we.eq(self.dac.stb),
  143
+			fifo.din.eq(fifo_in.raw_bits()),
  144
+			fifo_out.raw_bits().eq(fifo.dout),
162 145
 			self.busy.eq(0)
163 146
 		]
164 147
 
@@ -177,7 +160,7 @@ def __init__(self):
177 160
 				self.vga_b.eq(fifo_out.p0.b)
178 161
 			)
179 162
 		]
180  
-		self.comb += fifo_read_en.eq(pix_parity)
  163
+		self.comb += fifo.re.eq(pix_parity)
181 164
 
182 165
 def sim_fifo_gen():
183 166
 	while True:
103  verilog/generic/asfifo.v
... ...
@@ -1,103 +0,0 @@
1  
-/*
2  
- * This file is based on "Asynchronous FIFO" by Alex Claros F.,
3  
- * itself based on the article "Asynchronous FIFO in Virtex-II FPGAs"
4  
- * by Peter Alfke.
5  
- */
6  
-
7  
-module asfifo #(
8  
-	parameter data_width = 8,
9  
-	parameter address_width = 4,
10  
-	parameter fifo_depth = (1 << address_width)
11  
-) (
12  
-	/* Read port */
13  
-	output reg [data_width-1:0] data_out,
14  
-	output reg empty,
15  
-	input read_en,
16  
-	input clk_read,
17  
-	
18  
-	/* Write port */
19  
-	input [data_width-1:0] data_in,
20  
-	output reg full,
21  
-	input write_en,
22  
-	input clk_write,
23  
-	
24  
-	/* Asynchronous reset */
25  
-	input rst
26  
-);
27  
-
28  
-reg [data_width-1:0] mem[fifo_depth-1:0];
29  
-wire [address_width-1:0] write_index, read_index;
30  
-wire equal_addresses;
31  
-wire write_en_safe, read_en_safe;
32  
-wire set_status, clear_status;
33  
-reg status;
34  
-wire preset_full, preset_empty;
35  
-
36  
-reg [data_width-1:0] data_out0;
37  
-
38  
-always @(posedge clk_read) begin
39  
-	data_out0 <= mem[read_index];
40  
-	data_out <= data_out0;
41  
-end
42  
-
43  
-always @(posedge clk_write) begin
44  
-	if(write_en & !full)
45  
-		mem[write_index] <= data_in;
46  
-end
47  
-
48  
-assign write_en_safe = write_en & ~full;
49  
-assign read_en_safe = read_en & ~empty;
50  
-
51  
-asfifo_graycounter #(
52  
-	.width(address_width)
53  
-) counter_write (
54  
-	.gray_count(write_index),
55  
-	.ce(write_en_safe),
56  
-	.rst(rst),
57  
-	.clk(clk_write)
58  
-);
59  
-
60  
-asfifo_graycounter #(
61  
-	.width(address_width)
62  
-) counter_read (
63  
-	.gray_count(read_index),
64  
-	.ce(read_en_safe),
65  
-	.rst(rst),
66  
-	.clk(clk_read)
67  
-);
68  
-
69  
-assign equal_addresses = (write_index == read_index);
70  
-
71  
-assign set_status = (write_index[address_width-2] ~^ read_index[address_width-1]) &
72  
-	(write_index[address_width-1] ^ read_index[address_width-2]);
73  
-
74  
-assign clear_status = ((write_index[address_width-2] ^ read_index[address_width-1]) &
75  
-	(write_index[address_width-1] ~^ read_index[address_width-2]))
76  
-	| rst;
77  
-
78  
-always @(posedge clear_status, posedge set_status) begin
79  
-	if(clear_status)
80  
-		status <= 1'b0;
81  
-	else
82  
-		status <= 1'b1;
83  
-end
84  
-
85  
-assign preset_full = status & equal_addresses;
86  
-
87  
-always @(posedge clk_write, posedge preset_full) begin
88  
-	if(preset_full)
89  
-		full <= 1'b1;
90  
-	else
91  
-		full <= 1'b0;
92  
-end
93  
-
94  
-assign preset_empty = ~status & equal_addresses;
95  
-
96  
-always @(posedge clk_read, posedge preset_empty) begin
97  
-	if(preset_empty)
98  
-		empty <= 1'b1;
99  
-	else
100  
-		empty <= 1'b0;
101  
-end
102  
-
103  
-endmodule
29  verilog/generic/asfifo_graycounter.v
... ...
@@ -1,29 +0,0 @@
1  
-/*
2  
- * This file is based on "Asynchronous FIFO" by Alex Claros F.,
3  
- * itself based on the article "Asynchronous FIFO in Virtex-II FPGAs"
4  
- * by Peter Alfke.
5  
- */
6  
-
7  
-module asfifo_graycounter #(
8  
-	parameter width = 2
9  
-) (
10  
-	output reg [width-1:0] gray_count,
11  
-	input ce,
12  
-	input rst,
13  
-	input clk
14  
-);
15  
-
16  
-reg [width-1:0] binary_count;
17  
-
18  
-always @(posedge clk, posedge rst) begin
19  
-	if(rst) begin
20  
-		binary_count <= {width{1'b0}} + 1;
21  
-		gray_count <= {width{1'b0}};
22  
-	end else if(ce) begin
23  
-		binary_count <= binary_count + 1;
24  
-		gray_count <= {binary_count[width-1],
25  
-				binary_count[width-2:0] ^ binary_count[width-1:1]};
26  
-	end
27  
-end
28  
-
29  
-endmodule
0  verilog/generic/psync.v → verilog/minimac3/psync.v
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