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6  milkymist/asmicon/bankmachine.py
@@ -119,11 +119,13 @@ def get_fragment(self):
119 119
 			for slot in self.slots]
120 120
 		comb += multimux(rr.grant, mux_inputs, mux_outputs)
121 121
 		comb += [
122  
-			self.stb.eq(state == SLOT_PENDING),
  122
+			self.stb.eq(
  123
+				(self.slicer.bank(self.adr) == self.bankn) \
  124
+				& (state == SLOT_PENDING)),
123 125
 			rr.ce.eq(self.ack),
124 126
 			self.tag.eq(rr.grant)
125 127
 		]
126  
-		comb += [slot.process.eq((rr.grant == i) & self.stb & self.ack)
  128
+		comb += [If((rr.grant == i) & self.stb & self.ack, slot.process.eq(1))
127 129
 			for i, slot in enumerate(self.slots)]
128 130
 		
129 131
 		return Fragment(comb, sync) + rr.get_fragment()
4  milkymist/asmicon/multiplexer.py
@@ -53,11 +53,11 @@ def get_fragment(self):
53 53
 		outputs_filtered = [self.cmd.cas_n, self.cmd.ras_n, self.cmd.we_n]
54 54
 		ms = multimux(rr.grant, inputs_filtered, outputs_filtered)
55 55
 		comb += [
56  
-			self.cmd.stb.eq(stb & ((self.cmd.is_read == self.want_reads) | (self.cmd.is_write == self.want_writes))),
  56
+			self.cmd.stb.eq(stb & (self.cmd.is_read == self.want_reads) & (self.cmd.is_write == self.want_writes)),
57 57
 			If(self.cmd.stb, *ms)
58 58
 		]
59 59
 		
60  
-		comb += [req.ack.eq(self.cmd.stb & self.cmd.ack & rr.grant == i)
  60
+		comb += [If(self.cmd.stb & self.cmd.ack & (rr.grant == i), req.ack.eq(1))
61 61
 			for i, req in enumerate(self.requests)]
62 62
 		comb.append(rr.ce.eq(self.cmd.ack))
63 63
 		
31  tb/asmicon/asmicon.py
... ...
@@ -0,0 +1,31 @@
  1
+from migen.fhdl.structure import *
  2
+from migen.bus.asmibus import *
  3
+from migen.sim.generic import Simulator, TopLevel
  4
+from migen.sim.icarus import Runner
  5
+
  6
+from milkymist.asmicon import *
  7
+
  8
+from common import sdram_phy, sdram_geom, sdram_timing, DFILogger
  9
+
  10
+def my_generator():
  11
+	for x in range(100):
  12
+		t = TRead(x)
  13
+		yield t
  14
+
  15
+def main():
  16
+	dut = ASMIcon(sdram_phy, sdram_geom, sdram_timing)
  17
+	initiator = Initiator(dut.hub.get_port(), my_generator())
  18
+	dut.finalize()
  19
+	
  20
+	logger = DFILogger(dut.dfi)
  21
+	
  22
+	def end_simulation(s):
  23
+		s.interrupt = initiator.done
  24
+	
  25
+	fragment = dut.get_fragment() + initiator.get_fragment() + \
  26
+		logger.get_fragment() + \
  27
+		Fragment(sim=[end_simulation])
  28
+	sim = Simulator(fragment, Runner(keep_files=True), TopLevel("my.vcd"))
  29
+	sim.run()
  30
+
  31
+main()
77  tb/asmicon/common.py
@@ -15,6 +15,12 @@ def ns(t, margin=True):
15 15
 		t += clk_period_ns/2
16 16
 	return ceil(t/clk_period_ns)
17 17
 
  18
+sdram_phy = asmicon.PhySettings(
  19
+	dfi_d=64, 
  20
+	nphases=2,
  21
+	rdphase=0,
  22
+	wrphase=1
  23
+)
18 24
 sdram_geom = asmicon.GeomSettings(
19 25
 	bank_a=2,
20 26
 	row_a=13,
@@ -35,6 +41,34 @@ def ns(t, margin=True):
35 41
 	write_time=16
36 42
 )
37 43
 
  44
+def decode_sdram(ras_n, cas_n, we_n, bank, address):
  45
+	elts = []
  46
+	if not ras_n and cas_n and we_n:
  47
+		elts.append("ACTIVATE")
  48
+		elts.append("BANK " + str(bank))
  49
+		elts.append("ROW " + str(address))
  50
+	elif ras_n and not cas_n and we_n:
  51
+		elts.append("READ\t")
  52
+		elts.append("BANK " + str(bank))
  53
+		elts.append("COL " + str(address))
  54
+	elif ras_n and not cas_n and not we_n:
  55
+		elts.append("WRITE\t")
  56
+		elts.append("BANK " + str(bank))
  57
+		elts.append("COL " + str(address))
  58
+	elif ras_n and cas_n and not we_n:
  59
+		elts.append("BST")
  60
+	elif not ras_n and not cas_n and we_n:
  61
+		elts.append("AUTO REFRESH")
  62
+	elif not ras_n and cas_n and not we_n:
  63
+		elts.append("PRECHARGE")
  64
+		if address & 2**10:
  65
+			elts.append("ALL")
  66
+		else:
  67
+			elts.append("BANK " + str(bank))
  68
+	elif not ras_n and not cas_n and not we_n:
  69
+		elts.append("LMR")
  70
+	return elts
  71
+
38 72
 class CommandLogger:
39 73
 	def __init__(self, cmd, rw=False):
40 74
 		self.cmd = cmd
@@ -42,33 +76,8 @@ def __init__(self, cmd, rw=False):
42 76
 	
43 77
 	def do_simulation(self, s):
44 78
 		elts = ["@" + str(s.cycle_counter)]
45  
-		
46 79
 		cmdp = Proxy(s, self.cmd)
47  
-		if not cmdp.ras_n and cmdp.cas_n and cmdp.we_n:
48  
-			elts.append("ACTIVATE")
49  
-			elts.append("BANK " + str(cmdp.ba))
50  
-			elts.append("ROW " + str(cmdp.a))
51  
-		elif cmdp.ras_n and not cmdp.cas_n and cmdp.we_n:
52  
-			elts.append("READ\t")
53  
-			elts.append("BANK " + str(cmdp.ba))
54  
-			elts.append("COL " + str(cmdp.a))
55  
-		elif cmdp.ras_n and not cmdp.cas_n and not cmdp.we_n:
56  
-			elts.append("WRITE\t")
57  
-			elts.append("BANK " + str(cmdp.ba))
58  
-			elts.append("COL " + str(cmdp.a))
59  
-		elif cmdp.ras_n and cmdp.cas_n and not cmdp.we_n:
60  
-			elts.append("BST")
61  
-		elif not cmdp.ras_n and not cmdp.cas_n and cmdp.we_n:
62  
-			elts.append("AUTO REFRESH")
63  
-		elif not cmdp.ras_n and cmdp.cas_n and not cmdp.we_n:
64  
-			elts.append("PRECHARGE")
65  
-			if cmdp.a & 2**10:
66  
-				elts.append("ALL")
67  
-			else:
68  
-				elts.append("BANK " + str(cmdp.ba))
69  
-		elif not cmdp.ras_n and not cmdp.cas_n and not cmdp.we_n:
70  
-			elts.append("LMR")
71  
-		
  80
+		elts += decode_sdram(cmdp.ras_n, cmdp.cas_n, cmdp.we_n, cmdp.ba, cmdp.a)
72 81
 		if len(elts) > 1:
73 82
 			print("\t".join(elts))
74 83
 	
@@ -79,6 +88,22 @@ def get_fragment(self):
79 88
 			comb = []
80 89
 		return Fragment(comb, sim=[self.do_simulation])
81 90
 
  91
+class DFILogger:
  92
+	def __init__(self, dfi):
  93
+		self.dfi = dfi
  94
+	
  95
+	def do_simulation(self, s):
  96
+		dfip = Proxy(s, self.dfi)
  97
+		
  98
+		for i, p in enumerate(dfip.phases):
  99
+			elts = ["PH=" + str(i) + "\t @" + str(s.cycle_counter)]
  100
+			elts += decode_sdram(p.ras_n, p.cas_n, p.we_n, p.bank, p.address)
  101
+			if len(elts) > 1:
  102
+				print("\t".join(elts))
  103
+	
  104
+	def get_fragment(self):
  105
+		return Fragment(sim=[self.do_simulation])
  106
+		
82 107
 class SlotsLogger:
83 108
 	def __init__(self, slicer, slots):
84 109
 		self.slicer = slicer

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