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Showing with 39 additions and 1 deletion.
  1. +1 −1  tb/asmicon/asmicon.py
  2. +38 −0 tb/asmicon/asmicon_wb.py
2  tb/asmicon/asmicon.py
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@@ -25,7 +25,7 @@ def end_simulation(s):
fragment = dut.get_fragment() + initiator.get_fragment() + \
logger.get_fragment() + \
Fragment(sim=[end_simulation])
- sim = Simulator(fragment, Runner(keep_files=True), TopLevel("my.vcd"))
+ sim = Simulator(fragment, Runner(), TopLevel("my.vcd"))
sim.run()
main()
38 tb/asmicon/asmicon_wb.py
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@@ -0,0 +1,38 @@
+from migen.fhdl.structure import *
+from migen.bus import wishbone, wishbone2asmi, asmibus
+from migen.sim.generic import Simulator, TopLevel
+from migen.sim.icarus import Runner
+
+from milkymist.asmicon import *
+
+from common import sdram_phy, sdram_geom, sdram_timing, DFILogger
+
+l2_size = 8192 # in bytes
+
+def my_generator():
+ for x in range(100):
+ t = TRead(x)
+ yield t
+
+def main():
+ controller = ASMIcon(sdram_phy, sdram_geom, sdram_timing)
+ bridge = wishbone2asmi.WB2ASMI(l2_size//4, controller.hub.get_port())
+ controller.finalize()
+ initiator = wishbone.Initiator(my_generator())
+ conn = wishbone.InterconnectPointToPoint(initiator.bus, bridge.wishbone)
+
+ logger = DFILogger(controller.dfi)
+
+ def end_simulation(s):
+ s.interrupt = initiator.done
+
+ fragment = controller.get_fragment() + \
+ bridge.get_fragment() + \
+ initiator.get_fragment() + \
+ conn.get_fragment() + \
+ logger.get_fragment() + \
+ Fragment(sim=[end_simulation])
+ sim = Simulator(fragment, Runner(), TopLevel("my.vcd"))
+ sim.run()
+
+main()

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