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2  build.py
@@ -21,6 +21,8 @@ def main():
21 21
 	plat.request("ddram", obj=soc.ddrphy, name_map=lambda s: "sd_" + s)
22 22
 	plat.request("eth", obj=soc.minimac, name_map=lambda s: "phy_" + s)
23 23
 	plat.request("vga", obj=soc.fb, name_map=lambda s: "vga_" + s)
  24
+	plat.request("dvi_in", 0, obj=soc.dvisampler0)
  25
+	plat.request("dvi_in", 1, obj=soc.dvisampler1)
24 26
 	
25 27
 	# set extra constraints
26 28
 	plat.add_platform_command("""
18  common/csrbase.h
... ...
@@ -1,12 +1,16 @@
1 1
 #ifndef __CSRBASE_H
2 2
 #define __CSRBASE_H
3 3
 
4  
-#define UART_BASE		0xe0000000
5  
-#define DFII_BASE		0xe0000800
6  
-#define IDENTIFIER_BASE		0xe0001000
7  
-#define TIMER0_BASE		0xe0001800
8  
-#define MINIMAC_BASE		0xe0002000
9  
-#define FB_BASE			0xe0002800
10  
-#define ASMIPROBE_BASE		0xe0003000
  4
+#define UART_BASE			0xe0000000
  5
+#define DFII_BASE			0xe0000800
  6
+#define IDENTIFIER_BASE			0xe0001000
  7
+#define TIMER0_BASE			0xe0001800
  8
+#define MINIMAC_BASE			0xe0002000
  9
+#define FB_BASE				0xe0002800
  10
+#define ASMIPROBE_BASE			0xe0003000
  11
+#define DVISAMPLER0_BASE		0xe0003800
  12
+#define DVISAMPLER0_EDID_MEM_BASE	0xe0004000
  13
+#define DVISAMPLER1_BASE		0xe0004800
  14
+#define DVISAMPLER1_EDID_MEM_BASE	0xe0005000
11 15
 
12 16
 #endif /* __CSRBASE_H */
18  milkymist/dvisampler/__init__.py
... ...
@@ -0,0 +1,18 @@
  1
+from migen.fhdl.structure import *
  2
+from migen.fhdl.module import Module
  3
+from migen.bank.description import *
  4
+
  5
+from milkymist.dvisampler.edid import EDID
  6
+
  7
+class DVISampler(Module, AutoReg):
  8
+	def __init__(self, inversions=""):
  9
+		self.clk = Signal()
  10
+		for datan in "012":
  11
+			name = "data" + str(datan)
  12
+			if datan in inversions:
  13
+				name += "_n"
  14
+			setattr(self, name, Signal(name=name))
  15
+		
  16
+		self.submodules.edid = EDID()
  17
+		self.sda = self.edid.sda
  18
+		self.scl = self.edid.scl
182  milkymist/dvisampler/edid.py
... ...
@@ -0,0 +1,182 @@
  1
+from migen.fhdl.structure import *
  2
+from migen.fhdl.specials import Memory, Tristate
  3
+from migen.fhdl.module import Module
  4
+from migen.genlib.cdc import MultiReg
  5
+from migen.genlib.fsm import FSM
  6
+from migen.genlib.misc import chooser
  7
+from migen.bank.description import AutoReg
  8
+
  9
+_default_edid = [
  10
+	0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x3D, 0x17, 0x20, 0x11, 0x3E, 0x11, 0x00, 0x00,
  11
+	0x01, 0x17, 0x01, 0x03, 0x80, 0x30, 0x1B, 0x78, 0x08, 0x1D, 0xC5, 0xA4, 0x55, 0x54, 0xA0, 0x27,
  12
+	0x0C, 0x50, 0x54, 0x3F, 0xC0, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
  13
+	0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x88, 0x13, 0x20, 0x3C, 0x30, 0x58, 0x2D, 0x20, 0x58, 0x2C,
  14
+	0x45, 0x00, 0xE0, 0x0E, 0x11, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x4D, 0x31, 0x20,
  15
+	0x44, 0x56, 0x49, 0x20, 0x6D, 0x69, 0x78, 0x65, 0x72, 0x0A, 0x00, 0x00, 0x00, 0x10, 0x00, 0x32,
  16
+	0x4C, 0x1E, 0x53, 0x11, 0x00, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0x10,
  17
+	0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x00, 0x2C,
  18
+]
  19
+
  20
+class EDID(Module, AutoReg):
  21
+	def __init__(self, default=_default_edid):
  22
+		self.scl = Signal()
  23
+		self.sda = Signal()
  24
+
  25
+		self.specials.mem = Memory(8, 128, init=default)
  26
+
  27
+		###
  28
+
  29
+		scl_i = Signal()
  30
+		sda_i = Signal()
  31
+		sda_drv = Signal()
  32
+		_sda_drv_reg = Signal()
  33
+		_sda_i_async = Signal()
  34
+		self.sync += _sda_drv_reg.eq(sda_drv)
  35
+		self.specials += [
  36
+			MultiReg(self.scl, "ext", scl_i, "sys"),
  37
+			Tristate(self.sda, 0, _sda_drv_reg, _sda_i_async),
  38
+			MultiReg(_sda_i_async, "ext", sda_i, "sys")
  39
+		]
  40
+
  41
+		# FIXME: understand what is really going on here and get rid of that workaround
  42
+		for x in range(20):
  43
+			new_scl = Signal()
  44
+			self.sync += new_scl.eq(scl_i)
  45
+			scl_i = new_scl
  46
+		#
  47
+
  48
+		scl_r = Signal()
  49
+		sda_r = Signal()
  50
+		scl_rising = Signal()
  51
+		sda_rising = Signal()
  52
+		sda_falling = Signal()
  53
+		self.sync += [
  54
+			scl_r.eq(scl_i),
  55
+			sda_r.eq(sda_i)
  56
+		]
  57
+		self.comb += [
  58
+			scl_rising.eq(scl_i & ~scl_r),
  59
+			sda_rising.eq(sda_i & ~sda_r),
  60
+			sda_falling.eq(~sda_i & sda_r)
  61
+		]
  62
+
  63
+		start = Signal()
  64
+		self.comb += start.eq(scl_i & sda_falling)
  65
+
  66
+		din = Signal(8)
  67
+		counter = Signal(max=9)
  68
+		self.sync += [
  69
+			If(start, counter.eq(0)),
  70
+			If(scl_rising,
  71
+				If(counter == 8,
  72
+					counter.eq(0)
  73
+				).Else(
  74
+					counter.eq(counter + 1),
  75
+					din.eq(Cat(sda_i, din[:7]))
  76
+				)
  77
+			)
  78
+		]
  79
+
  80
+		is_read = Signal()
  81
+		update_is_read = Signal()
  82
+		self.sync += If(update_is_read, is_read.eq(din[0]))
  83
+
  84
+		offset_counter = Signal(max=128)
  85
+		oc_load = Signal()
  86
+		oc_inc = Signal()
  87
+		self.sync += [
  88
+			If(oc_load,
  89
+				offset_counter.eq(din)
  90
+			).Elif(oc_inc,
  91
+				offset_counter.eq(offset_counter + 1)
  92
+			)
  93
+		]
  94
+		rdport = self.mem.get_port()
  95
+		self.comb += rdport.adr.eq(offset_counter)
  96
+		data_bit = Signal()
  97
+
  98
+		zero_drv = Signal()
  99
+		data_drv = Signal()
  100
+		self.comb += If(zero_drv, sda_drv.eq(1)).Elif(data_drv, sda_drv.eq(~data_bit))
  101
+
  102
+		data_drv_en = Signal()
  103
+		data_drv_stop = Signal()
  104
+		self.sync += If(data_drv_en, data_drv.eq(1)).Elif(data_drv_stop, data_drv.eq(0))
  105
+		self.sync += If(data_drv_en, chooser(rdport.dat_r, counter, data_bit, 8, reverse=True))
  106
+
  107
+		states = ["WAIT_START",
  108
+			"RCV_ADDRESS", "ACK_ADDRESS0", "ACK_ADDRESS1", "ACK_ADDRESS2",
  109
+			"RCV_OFFSET", "ACK_OFFSET0", "ACK_OFFSET1", "ACK_OFFSET2",
  110
+			"READ", "ACK_READ"]
  111
+		fsm = FSM(*states)
  112
+		self.submodules += fsm
  113
+	
  114
+		fsm.act(fsm.RCV_ADDRESS,
  115
+			If(counter == 8,
  116
+				If(din[1:] == 0x50,
  117
+					update_is_read.eq(1),
  118
+					fsm.next_state(fsm.ACK_ADDRESS0)
  119
+				).Else(
  120
+					fsm.next_state(fsm.WAIT_START)
  121
+				)
  122
+			)
  123
+		)
  124
+		fsm.act(fsm.ACK_ADDRESS0,
  125
+			If(~scl_i, fsm.next_state(fsm.ACK_ADDRESS1))
  126
+		)
  127
+		fsm.act(fsm.ACK_ADDRESS1,
  128
+			zero_drv.eq(1),
  129
+			If(scl_i, fsm.next_state(fsm.ACK_ADDRESS2))
  130
+		)
  131
+		fsm.act(fsm.ACK_ADDRESS2,
  132
+			zero_drv.eq(1),
  133
+			If(~scl_i,
  134
+				If(is_read,
  135
+					fsm.next_state(fsm.READ)
  136
+				).Else(
  137
+					fsm.next_state(fsm.RCV_OFFSET)
  138
+				)
  139
+			)
  140
+		)
  141
+
  142
+		fsm.act(fsm.RCV_OFFSET,
  143
+			If(counter == 8,
  144
+				oc_load.eq(1),
  145
+				fsm.next_state(fsm.ACK_OFFSET0)
  146
+			)
  147
+		)
  148
+		fsm.act(fsm.ACK_OFFSET0,
  149
+			If(~scl_i, fsm.next_state(fsm.ACK_OFFSET1))
  150
+		)
  151
+		fsm.act(fsm.ACK_OFFSET1,
  152
+			zero_drv.eq(1),
  153
+			If(scl_i, fsm.next_state(fsm.ACK_OFFSET2))
  154
+		)
  155
+		fsm.act(fsm.ACK_OFFSET2,
  156
+			zero_drv.eq(1),
  157
+			If(~scl_i, fsm.next_state(fsm.RCV_ADDRESS))
  158
+		)
  159
+
  160
+		fsm.act(fsm.READ,
  161
+			If(~scl_i,
  162
+				If(counter == 8,
  163
+					data_drv_stop.eq(1),
  164
+					fsm.next_state(fsm.ACK_READ)
  165
+				).Else(
  166
+					data_drv_en.eq(1)
  167
+				)
  168
+			)
  169
+		)
  170
+		fsm.act(fsm.ACK_READ,
  171
+			If(scl_rising,
  172
+				oc_inc.eq(1),
  173
+				If(sda_i,
  174
+					fsm.next_state(fsm.WAIT_START)
  175
+				).Else(
  176
+					fsm.next_state(fsm.READ)
  177
+				)
  178
+			)
  179
+		)
  180
+
  181
+		for state in states:
  182
+			fsm.act(getattr(fsm, state), If(start, fsm.next_state(fsm.RCV_ADDRESS)))
2  software/bios/main.c
@@ -79,7 +79,7 @@ static void mr(char *startaddr, char *len)
79 79
 		return;
80 80
 	}
81 81
 	if(*len == 0) {
82  
-		length = 1;
  82
+		length = 4;
83 83
 	} else {
84 84
 		length = strtoul(len, &c, 0);
85 85
 		if(*c != 0) {
4  top.py
@@ -7,7 +7,7 @@
7 7
 from migen.bank import csrgen
8 8
 
9 9
 from milkymist import m1crg, lm32, norflash, uart, s6ddrphy, dfii, asmicon, \
10  
-	identifier, timer, minimac3, framebuffer, asmiprobe
  10
+	identifier, timer, minimac3, framebuffer, asmiprobe, dvisampler
11 11
 from cmacros import get_macros
12 12
 
13 13
 MHz = 1000000
@@ -119,6 +119,8 @@ def __init__(self):
119 119
 		self.submodules.timer0 = timer.Timer()
120 120
 		self.submodules.fb = framebuffer.Framebuffer(asmiport_fb)
121 121
 		self.submodules.asmiprobe = asmiprobe.ASMIprobe(self.asmicon.hub)
  122
+		self.submodules.dvisampler0 = dvisampler.DVISampler("02")
  123
+		self.submodules.dvisampler1 = dvisampler.DVISampler("02")
122 124
 
123 125
 		self.submodules.csrbankarray = csrgen.BankArray(self, csr_address_map)
124 126
 		self.submodules.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses())

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