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21  Makefile
... ...
@@ -1,21 +0,0 @@
1  
-RM ?= rm -f
2  
-
3  
-all: build/soc.bit build/soc.fpg
4  
-
5  
-build/soc.bit build/soc.bin:
6  
-	./build.py
7  
-
8  
-build/soc.fpg: build/soc.bin
9  
-	$(MAKE) -C tools
10  
-	tools/byteswap $< $@
11  
-
12  
-load: build/soc.bit
13  
-	jtag -n load.jtag
14  
-
15  
-flash: build/soc.fpg
16  
-	m1nor-ng build/soc.fpg
17  
-
18  
-clean:
19  
-	$(RM) -r build/*
20  
-
21  
-.PHONY: all load clean flash
27  README
@@ -2,17 +2,16 @@
2 2
 ------------------------------
3 3
 
4 4
 This is the next-generation Milkymist(tm) system-on-chip design,
5  
-introducing two key innovations:
  5
+introducing two key features:
6 6
  * Built on the powerful Migen VLSI logic design system.
7  
- * Increased system memory performance thanks to a new architecture
8  
-   (ASMI) containing a transaction-reordering and superscalar controller.
  7
+ * Increased system memory performance thanks to LASMI.
9 8
 
10  
-The Milkymist-NG SoC supports the Milkymist One board. Obtain yours at:
11  
-  http://milkymist.org
  9
+This translates to more development productivity, better video resolution
  10
+and quality, ease of designing complex hardware accelerators, and much
  11
+more flexibility in hardware designs.
12 12
 
13  
-Note that the -NG version is still experimental work in progress. For the
14  
-production version of Milkymist SoC, visit:
15  
-  https://github.com/milkymist/milkymist
  13
+The Milkymist-NG SoC supports the Mixxeo and the Milkymist One.
  14
+Obtain yours at http://milkymist.org
16 15
 
17 16
 [> Instructions (software)
18 17
 --------------------------
@@ -50,15 +49,11 @@ First, download and install Migen from:
50 49
   https://github.com/milkymist/migen
51 50
 
52 51
 Once this is done, build the bitstream with:
53  
-  make
54  
-This will generate the build/soc.bit programming file.
55  
-Use:
56  
-  make load
57  
-to load it with UrJTAG.
  52
+  ./make.py [-p <platform>] -l
  53
+This will generate the build/soc-<platform>.bit programming file
  54
+and load it with UrJTAG.
58 55
 
59  
-The SoC expects a bootloader to be located in flash at 0x860000, just
60  
-like the legacy SoC did. However, there is no binary compatibility and a
61  
-new BIOS needs to be built and flashed for the -NG SoC.
  56
+A new BIOS needs to be built and flashed for the -NG SoC.
62 57
 
63 58
 Enjoy!
64 59
 
77  build.py
... ...
@@ -1,77 +0,0 @@
1  
-#!/usr/bin/env python3
2  
-
3  
-import os
4  
-
5  
-from mibuild.platforms import m1
6  
-from mibuild.tools import write_to_file
7  
-
8  
-from milkymist import cif
9  
-
10  
-import top
11  
-
12  
-def main():
13  
-	platform = m1.Platform()
14  
-	soc = top.SoC(platform)
15  
-	
16  
-	platform.add_platform_command("""
17  
-NET "{clk50}" TNM_NET = "GRPclk50";
18  
-TIMESPEC "TSclk50" = PERIOD "GRPclk50" 20 ns HIGH 50%;
19  
-""", clk50=platform.lookup_request("clk50"))
20  
-
21  
-	platform.add_platform_command("""
22  
-INST "m1crg/wr_bufpll" LOC = "BUFPLL_X0Y2";
23  
-INST "m1crg/rd_bufpll" LOC = "BUFPLL_X0Y3";
24  
-
25  
-PIN "m1crg/bufg_x1.O" CLOCK_DEDICATED_ROUTE = FALSE;
26  
-""")
27  
-
28  
-	if hasattr(soc, "fb"):
29  
-		platform.add_platform_command("""
30  
-NET "vga_clk" TNM_NET = "GRPvga_clk";
31  
-NET "sys_clk" TNM_NET = "GRPsys_clk";
32  
-TIMESPEC "TSise_sucks1" = FROM "GRPvga_clk" TO "GRPsys_clk" TIG;
33  
-TIMESPEC "TSise_sucks2" = FROM "GRPsys_clk" TO "GRPvga_clk" TIG;
34  
-""")
35  
-
36  
-	if hasattr(soc, "minimac"):
37  
-		platform.add_platform_command("""
38  
-NET "{phy_rx_clk}" TNM_NET = "GRPphy_rx_clk";
39  
-NET "{phy_tx_clk}" TNM_NET = "GRPphy_tx_clk";
40  
-TIMESPEC "TSphy_rx_clk" = PERIOD "GRPphy_rx_clk" 40 ns HIGH 50%;
41  
-TIMESPEC "TSphy_tx_clk" = PERIOD "GRPphy_tx_clk" 40 ns HIGH 50%;
42  
-TIMESPEC "TSphy_tx_clk_io" = FROM "GRPphy_tx_clk" TO "PADS" 10 ns;
43  
-TIMESPEC "TSphy_rx_clk_io" = FROM "PADS" TO "GRPphy_rx_clk" 10 ns;
44  
-""",
45  
-		phy_rx_clk=platform.lookup_request("eth_clocks").rx,
46  
-		phy_tx_clk=platform.lookup_request("eth_clocks").tx,)
47  
-
48  
-	if hasattr(soc, "dvisampler0"):
49  
-		platform.add_platform_command("""
50  
-NET "{dviclk0}" TNM_NET = "GRPdviclk0";
51  
-NET "{dviclk0}" CLOCK_DEDICATED_ROUTE = FALSE;
52  
-TIMESPEC "TSdviclk0" = PERIOD "GRPdviclk0" 26.7 ns HIGH 50%;
53  
-""", dviclk0=platform.lookup_request("dvi_in", 0).clk)
54  
-	if hasattr(soc, "dvisampler1"):
55  
-		platform.add_platform_command("""
56  
-NET "{dviclk1}" TNM_NET = "GRPdviclk1";
57  
-NET "{dviclk1}" CLOCK_DEDICATED_ROUTE = FALSE;
58  
-TIMESPEC "TSdviclk1" = PERIOD "GRPdviclk1" 26.7 ns HIGH 50%;
59  
-""", dviclk1=platform.lookup_request("dvi_in", 1).clk)
60  
-	
61  
-	for d in ["m1crg", "s6ddrphy", "minimac3"]:
62  
-		platform.add_source_dir(os.path.join("verilog", d))
63  
-	platform.add_sources(os.path.join("verilog", "lm32", "submodule", "rtl"), 
64  
-		"lm32_cpu.v", "lm32_instruction_unit.v", "lm32_decoder.v",
65  
-		"lm32_load_store_unit.v", "lm32_adder.v", "lm32_addsub.v", "lm32_logic_op.v",
66  
-		"lm32_shifter.v", "lm32_multiplier.v", "lm32_mc_arithmetic.v",
67  
-		"lm32_interrupt.v", "lm32_ram.v", "lm32_dp_ram.v", "lm32_icache.v",
68  
-		"lm32_dcache.v", "lm32_top.v", "lm32_debug.v", "lm32_jtag.v", "jtag_cores.v",
69  
-		"jtag_tap_spartan6.v", "lm32_itlb.v", "lm32_dtlb.v")
70  
-	platform.add_sources(os.path.join("verilog", "lm32"), "lm32_config.v")
71  
-
72  
-	platform.build_cmdline(soc, build_name="soc")
73  
-	csr_header = cif.get_csr_header(soc.csr_base, soc.csrbankarray, soc.interrupt_map)
74  
-	write_to_file("software/include/hw/csr.h", csr_header)
75  
-
76  
-if __name__ == "__main__":
77  
-	main()
14  jtag.py
... ...
@@ -0,0 +1,14 @@
  1
+import subprocess
  2
+
  3
+def load(bitstream):
  4
+	cmds = """cable milkymist
  5
+detect
  6
+pld load {bitstream}
  7
+quit
  8
+""".format(bitstream=bitstream)
  9
+	process = subprocess.Popen("jtag", stdin=subprocess.PIPE)
  10
+	process.stdin.write(cmds.encode("ASCII"))
  11
+	process.communicate()
  12
+
  13
+def flash(bitstream):
  14
+	subprocess.call(["m1nor-ng", bitstream])
3  load.jtag
... ...
@@ -1,3 +0,0 @@
1  
-cable milkymist
2  
-detect
3  
-pld load build/soc.bit
67  make.py
... ...
@@ -0,0 +1,67 @@
  1
+#!/usr/bin/env python3
  2
+
  3
+import argparse, os, importlib, subprocess
  4
+
  5
+from mibuild.tools import write_to_file
  6
+
  7
+from milkymist import cif
  8
+import top, jtag
  9
+
  10
+def build(platform_name, build_bitstream, build_header):
  11
+	platform_module = importlib.import_module("mibuild.platforms."+platform_name)
  12
+	platform = platform_module.Platform()
  13
+	soc = top.SoC(platform, platform_name)
  14
+	
  15
+	platform.add_platform_command("""
  16
+INST "mxcrg/wr_bufpll" LOC = "BUFPLL_X0Y2";
  17
+INST "mxcrg/rd_bufpll" LOC = "BUFPLL_X0Y3";
  18
+
  19
+PIN "mxcrg/bufg_x1.O" CLOCK_DEDICATED_ROUTE = FALSE;
  20
+""")
  21
+
  22
+	if hasattr(soc, "fb"):
  23
+		platform.add_platform_command("""
  24
+NET "vga_clk" TNM_NET = "GRPvga_clk";
  25
+NET "sys_clk" TNM_NET = "GRPsys_clk";
  26
+TIMESPEC "TSise_sucks1" = FROM "GRPvga_clk" TO "GRPsys_clk" TIG;
  27
+TIMESPEC "TSise_sucks2" = FROM "GRPsys_clk" TO "GRPvga_clk" TIG;
  28
+""")
  29
+
  30
+	for d in ["mxcrg", "s6ddrphy", "minimac3"]:
  31
+		platform.add_source_dir(os.path.join("verilog", d))
  32
+	platform.add_sources(os.path.join("verilog", "lm32", "submodule", "rtl"), 
  33
+		"lm32_cpu.v", "lm32_instruction_unit.v", "lm32_decoder.v",
  34
+		"lm32_load_store_unit.v", "lm32_adder.v", "lm32_addsub.v", "lm32_logic_op.v",
  35
+		"lm32_shifter.v", "lm32_multiplier.v", "lm32_mc_arithmetic.v",
  36
+		"lm32_interrupt.v", "lm32_ram.v", "lm32_dp_ram.v", "lm32_icache.v",
  37
+		"lm32_dcache.v", "lm32_top.v", "lm32_debug.v", "lm32_jtag.v", "jtag_cores.v",
  38
+		"jtag_tap_spartan6.v", "lm32_itlb.v", "lm32_dtlb.v")
  39
+	platform.add_sources(os.path.join("verilog", "lm32"), "lm32_config.v")
  40
+
  41
+	if build_bitstream:
  42
+		build_name = "soc-"+platform_name
  43
+		platform.build(soc, build_name=build_name)
  44
+		subprocess.call(["tools/byteswap", build_name+".bin", build_name+".fpg"])
  45
+	else:
  46
+		soc.finalize()
  47
+	if build_header:
  48
+		csr_header = cif.get_csr_header(soc.csr_base, soc.csrbankarray, soc.interrupt_map)
  49
+		write_to_file("software/include/hw/csr.h", csr_header)
  50
+
  51
+def main():
  52
+	parser = argparse.ArgumentParser(description="milkymist-ng - a high performance SoC built on Migen technology.")
  53
+	parser.add_argument("-p", "--platform", default="mixxeo", help="platform to build for")
  54
+	parser.add_argument("-B", "--no-bitstream", default=False, action="store_true", help="do not build bitstream file")
  55
+	parser.add_argument("-H", "--no-header", default=False, action="store_true", help="do not build C header file with CSR/IRQ defs")
  56
+	parser.add_argument("-l", "--load", default=False, action="store_true", help="load bitstream to SRAM")
  57
+	parser.add_argument("-f", "--flash", default=False, action="store_true", help="load bitstream to flash")
  58
+	args = parser.parse_args()
  59
+
  60
+	build(args.platform, not args.no_bitstream, not args.no_header)
  61
+	if args.load:
  62
+		jtag.load("build/soc-"+args.platform+".bit")
  63
+	if args.flash:
  64
+		jtag.flash("build/soc-"+args.platform+".fpg")
  65
+
  66
+if __name__ == "__main__":
  67
+	main()
18  milkymist/dvisampler/__init__.py
@@ -19,11 +19,19 @@ def __init__(self, pads, asmiport, n_dma_slots=2):
19 19
 		for datan in range(3):
20 20
 			name = "data" + str(datan)
21 21
 			invert = False
22  
-			try:
23  
-				s = getattr(pads, name)
24  
-			except AttributeError:
25  
-				s = getattr(pads, name + "_n")
26  
-				invert = True
  22
+			if hasattr(pads, name + "_p"):
  23
+				s = Signal()
  24
+				self.specials += Instance("IBUFDS",
  25
+					Instance.Input("I", getattr(pads, name + "_p")),
  26
+					Instance.Input("IB", getattr(pads, name + "_n")),
  27
+					Instance.Output("O", s)		
  28
+				)
  29
+			else:
  30
+				try:
  31
+					s = getattr(pads, name)
  32
+				except AttributeError:
  33
+					s = getattr(pads, name + "_n")
  34
+					invert = True
27 35
 			
28 36
 			cap = DataCapture(8, invert)
29 37
 			setattr(self.submodules, name + "_cap", cap)
12  milkymist/dvisampler/clocking.py
@@ -16,6 +16,16 @@ def __init__(self, pads):
16 16
 
17 17
 		###
18 18
 
  19
+		if hasattr(pads, "clk_p"):
  20
+			clkin = Signal()
  21
+			self.specials += Instance("IBUFDS",
  22
+				Instance.Input("I", pads.clk_p),
  23
+				Instance.Input("IB", pads.clk_n),
  24
+				Instance.Output("O", clkin)		
  25
+			)
  26
+		else:
  27
+			clkin = pads.clk
  28
+
19 29
 		clkfbout = Signal()
20 30
 		pll_locked = Signal()
21 31
 		pll_clk0 = Signal()
@@ -39,7 +49,7 @@ def __init__(self, pads):
39 49
 			Instance.Output("CLKOUT3", pll_clk3),
40 50
 			Instance.Output("LOCKED", pll_locked),
41 51
 			Instance.Input("CLKFBIN", clkfbout),
42  
-			Instance.Input("CLKIN", pads.clk),
  52
+			Instance.Input("CLKIN", clkin),
43 53
 			Instance.Input("RST", self._r_pll_reset.storage)
44 54
 		)
45 55
 
4  milkymist/m1crg/__init__.py → milkymist/mxcrg/__init__.py
@@ -3,7 +3,7 @@
3 3
 from migen.fhdl.std import *
4 4
 from migen.bank.description import *
5 5
 
6  
-class M1CRG(Module, AutoCSR):
  6
+class MXCRG(Module, AutoCSR):
7 7
 	def __init__(self, pads, outfreq1x):
8 8
 		self.clock_domains.cd_sys = ClockDomain()
9 9
 		self.clock_domains.cd_sys2x_270 = ClockDomain()
@@ -32,7 +32,7 @@ def __init__(self, pads, outfreq1x):
32 32
 		vga_progdone = Signal()
33 33
 		vga_locked = Signal()
34 34
 
35  
-		self.specials += Instance("m1crg",
  35
+		self.specials += Instance("mxcrg",
36 36
 			Instance.Parameter("in_period", in_period),
37 37
 			Instance.Parameter("f_mult", ratio.numerator),
38 38
 			Instance.Parameter("f_div", ratio.denominator),
26  top.py
@@ -6,8 +6,9 @@
6 6
 from migen.bus import wishbone, csr, lasmibus, dfi
7 7
 from migen.bus import wishbone2lasmi, wishbone2csr
8 8
 from migen.bank import csrgen
  9
+from mibuild.generic_platform import ConstraintError
9 10
 
10  
-from milkymist import m1crg, lm32, norflash, uart, s6ddrphy, dfii, lasmicon, \
  11
+from milkymist import mxcrg, lm32, norflash, uart, s6ddrphy, dfii, lasmicon, \
11 12
 	identifier, timer, minimac3, framebuffer, dvisampler, \
12 13
 	counteradc, gpio
13 14
 from milkymist.cif import get_macros
@@ -51,10 +52,14 @@ def ns(t, margin=True):
51 52
 	write_time=16
52 53
 )
53 54
 
54  
-class M1ClockPads:
  55
+class MXClockPads:
55 56
 	def __init__(self, platform):
56 57
 		self.clk50 = platform.request("clk50")
57  
-		self.trigger_reset = platform.request("user_btn", 1)
  58
+		self.trigger_reset = 0
  59
+		try:
  60
+			self.trigger_reset = platform.request("user_btn", 1)
  61
+		except ConstraintError:
  62
+			pass
58 63
 		self.norflash_rst_n = platform.request("norflash_rst_n")
59 64
 		self.vga_clk = platform.request("vga_clock")
60 65
 		ddram_clock = platform.request("ddram_clock")
@@ -93,7 +98,7 @@ class SoC(Module):
93 98
 		"dvisampler1":	4,
94 99
 	}
95 100
 
96  
-	def __init__(self, platform):
  101
+	def __init__(self, platform, platform_name):
97 102
 		#
98 103
 		# LASMI
99 104
 		#
@@ -142,18 +147,19 @@ def __init__(self, platform):
142 147
 		#
143 148
 		# CSR
144 149
 		#
145  
-		self.submodules.crg = m1crg.M1CRG(M1ClockPads(platform), clk_freq)
  150
+		self.submodules.crg = mxcrg.MXCRG(MXClockPads(platform), clk_freq)
146 151
 		self.submodules.uart = uart.UART(platform.request("serial"), clk_freq, baud=115200)
147 152
 		self.submodules.identifier = identifier.Identifier(0x4D31, version, int(clk_freq))
148 153
 		self.submodules.timer0 = timer.Timer()
149 154
 		self.submodules.fb = framebuffer.MixFramebuffer(platform.request("vga"), lasmim_fb0, lasmim_fb1)
150 155
 		self.submodules.dvisampler0 = dvisampler.DVISampler(platform.request("dvi_in", 0), lasmim_dvi0)
151 156
 		self.submodules.dvisampler1 = dvisampler.DVISampler(platform.request("dvi_in", 1), lasmim_dvi1)
152  
-		pots_pads = platform.request("dvi_pots")
153  
-		self.submodules.pots = counteradc.CounterADC(pots_pads.charge,
154  
-			[pots_pads.blackout, pots_pads.crossfade])
155  
-		self.submodules.buttons = gpio.GPIOIn(Cat(platform.request("user_btn", 0), platform.request("user_btn", 2)))
156  
-		self.submodules.leds = gpio.GPIOOut(Cat(*[platform.request("user_led", i) for i in range(2)]))
  157
+		if platform_name == "m1":
  158
+			pots_pads = platform.request("dvi_pots")
  159
+			self.submodules.pots = counteradc.CounterADC(pots_pads.charge,
  160
+				[pots_pads.blackout, pots_pads.crossfade])
  161
+			self.submodules.buttons = gpio.GPIOIn(Cat(platform.request("user_btn", 0), platform.request("user_btn", 2)))
  162
+			self.submodules.leds = gpio.GPIOOut(Cat(*[platform.request("user_led", i) for i in range(2)]))
157 163
 
158 164
 		self.submodules.csrbankarray = csrgen.BankArray(self,
159 165
 			lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override])
6  verilog/m1crg/m1crg.v → verilog/mxcrg/mxcrg.v
... ...
@@ -1,4 +1,4 @@
1  
-module m1crg #(
  1
+module mxcrg #(
2 2
 	parameter in_period = 0.0,
3 3
 	parameter f_mult = 0,
4 4
 	parameter f_div = 0,
@@ -56,6 +56,8 @@ always @(posedge sys_clk) begin
56 56
 	sys_rst <= rst_debounce != 20'd0;
57 57
 end
58 58
 
  59
+initial rst_debounce <= 20'hFFFFF;
  60
+
59 61
 /*
60 62
  * We must release the Flash reset before the system reset
61 63
  * because the Flash needs some time to come out of reset
@@ -74,6 +76,8 @@ always @(posedge sys_clk) begin
74 76
 		flash_rstcounter <= flash_rstcounter + 8'd1;
75 77
 end
76 78
 
  79
+initial flash_rstcounter <= 8'd0;
  80
+
77 81
 assign norflash_rst_n = flash_rstcounter[7];
78 82
 
79 83
 /*

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