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5 milkymist/dvisampler/__init__.py
View
@@ -17,9 +17,10 @@ def __init__(self, inversions=""):
for datan in "012":
name = "data" + str(datan)
- cap = DataCapture(8)
+ invert = datan in inversions
+ cap = DataCapture(8, invert)
setattr(self.submodules, name + "_cap", cap)
- if datan in inversions:
+ if invert:
name += "_n"
s = Signal(name=name)
setattr(self, name, s)
21 milkymist/dvisampler/clocking.py
View
@@ -66,18 +66,17 @@ def __init__(self):
self.specials += MultiReg(locked_async, self.locked, "sys")
self.comb += self._r_locked.field.w.eq(self.locked)
- # sychronize pix5x reset
- # this reset is also sampled in the sys clock domain, also guarantee
- # a sufficient minimum pulse width.
- pix5x_rst_n = 1
- for i in range(5):
- new_pix5x_rst_n = Signal()
+ # sychronize pix+pix5x reset
+ pix_rst_n = 1
+ for i in range(2):
+ new_pix_rst_n = Signal()
self.specials += Instance("FDCE",
- Instance.Input("D", pix5x_rst_n),
+ Instance.Input("D", pix_rst_n),
Instance.Input("CE", 1),
- Instance.Input("C", ClockSignal("pix5x")),
+ Instance.Input("C", ClockSignal("pix")),
Instance.Input("CLR", ~locked_async),
- Instance.Output("Q", new_pix5x_rst_n)
+ Instance.Output("Q", new_pix_rst_n)
)
- pix5x_rst_n = new_pix5x_rst_n
- self.comb += self._cd_pix5x.rst.eq(~pix5x_rst_n)
+ pix_rst_n = new_pix_rst_n
+ self.comb += self._cd_pix.rst.eq(~pix_rst_n)
+ self.comb += self._cd_pix5x.rst.eq(~pix_rst_n)
26 milkymist/dvisampler/datacapture.py
View
@@ -5,11 +5,10 @@
from migen.bank.description import *
class DataCapture(Module, AutoReg):
- def __init__(self, ntbits):
+ def __init__(self, ntbits, invert):
self.pad = Signal()
self.serdesstrobe = Signal()
- self.d0 = Signal() # pix5x clock domain
- self.d1 = Signal() # pix5x clock domain
+ self.d = Signal(10)
self._r_dly_ctl = RegisterRaw(4)
self._r_dly_busy = RegisterField(1, READ_ONLY, WRITE_ONLY)
@@ -42,7 +41,9 @@ def __init__(self, ntbits):
Instance.Input("T", 1)
)
+ d0 = Signal()
d0p = Signal()
+ d1 = Signal()
d1p = Signal()
self.specials += Instance("ISERDES2",
Instance.Parameter("BITSLIP_ENABLE", "FALSE"),
@@ -50,9 +51,9 @@ def __init__(self, ntbits):
Instance.Parameter("DATA_WIDTH", 4),
Instance.Parameter("INTERFACE_TYPE", "RETIMED"),
Instance.Parameter("SERDES_MODE", "NONE"),
- Instance.Output("Q4", self.d0),
+ Instance.Output("Q4", d0),
Instance.Output("Q3", d0p),
- Instance.Output("Q2", self.d1),
+ Instance.Output("Q2", d1),
Instance.Output("Q1", d1p),
Instance.Input("BITSLIP", 0),
Instance.Input("CE0", 1),
@@ -75,8 +76,8 @@ def __init__(self, ntbits):
self.sync.pix5x += [
If(reset_lateness,
lateness.eq(2**(ntbits - 1))
- ).Elif(~delay_busy & ~too_late & ~too_early & (self.d0 != self.d1),
- If(self.d0,
+ ).Elif(~delay_busy & ~too_late & ~too_early & (d0 != d1),
+ If(d0,
# 1 -----> 0
# d0p
If(d0p,
@@ -146,3 +147,14 @@ def __init__(self, ntbits):
reset_lateness.eq(self.do_reset_lateness.o),
self.do_reset_lateness.i.eq(self._r_phase_reset.re)
]
+
+ # 2:10 deserialization
+ d0i = Signal()
+ d1i = Signal()
+ self.comb += [
+ d0i.eq(d0 ^ invert),
+ d1i.eq(d1 ^ invert)
+ ]
+ dsr = Signal(10)
+ self.sync.pix5x += dsr.eq(Cat(dsr[2:], d0i, d1i))
+ self.sync.pix += self.d.eq(dsr)

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