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5  milkymist/dvisampler/__init__.py
@@ -17,9 +17,10 @@ def __init__(self, inversions=""):
17 17
 
18 18
 		for datan in "012":
19 19
 			name = "data" + str(datan)
20  
-			cap = DataCapture(8)
  20
+			invert = datan in inversions
  21
+			cap = DataCapture(8, invert)
21 22
 			setattr(self.submodules, name + "_cap", cap)
22  
-			if datan in inversions:
  23
+			if invert:
23 24
 				name += "_n"
24 25
 			s = Signal(name=name)
25 26
 			setattr(self, name, s)
21  milkymist/dvisampler/clocking.py
@@ -66,18 +66,17 @@ def __init__(self):
66 66
 		self.specials += MultiReg(locked_async, self.locked, "sys")
67 67
 		self.comb += self._r_locked.field.w.eq(self.locked)
68 68
 
69  
-		# sychronize pix5x reset
70  
-		# this reset is also sampled in the sys clock domain, also guarantee
71  
-		# a sufficient minimum pulse width.
72  
-		pix5x_rst_n = 1
73  
-		for i in range(5):
74  
-			new_pix5x_rst_n = Signal()
  69
+		# sychronize pix+pix5x reset
  70
+		pix_rst_n = 1
  71
+		for i in range(2):
  72
+			new_pix_rst_n = Signal()
75 73
 			self.specials += Instance("FDCE",
76  
-				Instance.Input("D", pix5x_rst_n),
  74
+				Instance.Input("D", pix_rst_n),
77 75
 				Instance.Input("CE", 1),
78  
-				Instance.Input("C", ClockSignal("pix5x")),
  76
+				Instance.Input("C", ClockSignal("pix")),
79 77
 				Instance.Input("CLR", ~locked_async),
80  
-				Instance.Output("Q", new_pix5x_rst_n)
  78
+				Instance.Output("Q", new_pix_rst_n)
81 79
 			)
82  
-			pix5x_rst_n = new_pix5x_rst_n
83  
-		self.comb += self._cd_pix5x.rst.eq(~pix5x_rst_n)
  80
+			pix_rst_n = new_pix_rst_n
  81
+		self.comb += self._cd_pix.rst.eq(~pix_rst_n)
  82
+		self.comb += self._cd_pix5x.rst.eq(~pix_rst_n)
26  milkymist/dvisampler/datacapture.py
@@ -5,11 +5,10 @@
5 5
 from migen.bank.description import *
6 6
 
7 7
 class DataCapture(Module, AutoReg):
8  
-	def __init__(self, ntbits):
  8
+	def __init__(self, ntbits, invert):
9 9
 		self.pad = Signal()
10 10
 		self.serdesstrobe = Signal()
11  
-		self.d0 = Signal() # pix5x clock domain
12  
-		self.d1 = Signal() # pix5x clock domain
  11
+		self.d = Signal(10)
13 12
 
14 13
 		self._r_dly_ctl = RegisterRaw(4)
15 14
 		self._r_dly_busy = RegisterField(1, READ_ONLY, WRITE_ONLY)
@@ -42,7 +41,9 @@ def __init__(self, ntbits):
42 41
 			Instance.Input("T", 1)
43 42
 		)
44 43
 
  44
+		d0 = Signal()
45 45
 		d0p = Signal()
  46
+		d1 = Signal()
46 47
 		d1p = Signal()
47 48
 		self.specials += Instance("ISERDES2",
48 49
 			Instance.Parameter("BITSLIP_ENABLE", "FALSE"),
@@ -50,9 +51,9 @@ def __init__(self, ntbits):
50 51
 			Instance.Parameter("DATA_WIDTH", 4),
51 52
 			Instance.Parameter("INTERFACE_TYPE", "RETIMED"),
52 53
 			Instance.Parameter("SERDES_MODE", "NONE"),
53  
-			Instance.Output("Q4", self.d0),
  54
+			Instance.Output("Q4", d0),
54 55
 			Instance.Output("Q3", d0p),
55  
-			Instance.Output("Q2", self.d1),
  56
+			Instance.Output("Q2", d1),
56 57
 			Instance.Output("Q1", d1p),
57 58
 			Instance.Input("BITSLIP", 0),
58 59
 			Instance.Input("CE0", 1),
@@ -75,8 +76,8 @@ def __init__(self, ntbits):
75 76
 		self.sync.pix5x += [
76 77
 			If(reset_lateness,
77 78
 				lateness.eq(2**(ntbits - 1))
78  
-			).Elif(~delay_busy & ~too_late & ~too_early & (self.d0 != self.d1),
79  
-				If(self.d0,
  79
+			).Elif(~delay_busy & ~too_late & ~too_early & (d0 != d1),
  80
+				If(d0,
80 81
 					# 1 -----> 0
81 82
 					#    d0p
82 83
 					If(d0p,
@@ -146,3 +147,14 @@ def __init__(self, ntbits):
146 147
 			reset_lateness.eq(self.do_reset_lateness.o),
147 148
 			self.do_reset_lateness.i.eq(self._r_phase_reset.re)
148 149
 		]
  150
+
  151
+		# 2:10 deserialization
  152
+		d0i = Signal()
  153
+		d1i = Signal()
  154
+		self.comb += [
  155
+			d0i.eq(d0 ^ invert),
  156
+			d1i.eq(d1 ^ invert)
  157
+		]
  158
+		dsr = Signal(10)
  159
+		self.sync.pix5x += dsr.eq(Cat(dsr[2:], d0i, d1i))
  160
+		self.sync.pix += self.d.eq(dsr)

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