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Nov 14, 2012
Sébastien Bourdeauducq lm32: split lm32_include.v d15d982
Michael Walle lm32: replace $clog2 with macro
Unfortunately, XST does not support $clog2 with the localparam keyword
(the parameter keyword works just fine). Define a macro which replaces the
call with a constant function.

This commit can be reverted if the bug in XST is fixed.

Signed-off-by: Michael Walle <michael@walle.cc>
a0ff666
50  verilog/lm32/lm32_config.v
... ...
@@ -0,0 +1,50 @@
  1
+`ifdef LM32_CONFIG_V
  2
+`else
  3
+`define LM32_CONFIG_V
  4
+
  5
+`define CFG_EBA_RESET 32'h00860000
  6
+`define CFG_DEBA_RESET 32'h10000000
  7
+
  8
+`define CFG_PL_MULTIPLY_ENABLED
  9
+`define CFG_PL_BARREL_SHIFT_ENABLED
  10
+`define CFG_SIGN_EXTEND_ENABLED
  11
+`define CFG_MC_DIVIDE_ENABLED
  12
+`define CFG_EBR_POSEDGE_REGISTER_FILE
  13
+
  14
+`define CFG_ICACHE_ENABLED
  15
+`define CFG_ICACHE_ASSOCIATIVITY   1
  16
+`define CFG_ICACHE_SETS            256
  17
+`define CFG_ICACHE_BYTES_PER_LINE  16
  18
+`define CFG_ICACHE_BASE_ADDRESS    32'h0
  19
+`define CFG_ICACHE_LIMIT           32'h7fffffff
  20
+
  21
+`define CFG_DCACHE_ENABLED
  22
+`define CFG_DCACHE_ASSOCIATIVITY   1
  23
+`define CFG_DCACHE_SETS            256
  24
+`define CFG_DCACHE_BYTES_PER_LINE  16
  25
+`define CFG_DCACHE_BASE_ADDRESS    32'h0
  26
+`define CFG_DCACHE_LIMIT           32'h7fffffff
  27
+
  28
+// Enable Debugging
  29
+//`define CFG_JTAG_ENABLED
  30
+//`define CFG_JTAG_UART_ENABLED
  31
+//`define CFG_DEBUG_ENABLED
  32
+//`define CFG_HW_DEBUG_ENABLED
  33
+//`define CFG_ROM_DEBUG_ENABLED
  34
+//`define CFG_BREAKPOINTS 32'h4
  35
+//`define CFG_WATCHPOINTS 32'h4
  36
+//`define CFG_EXTERNAL_BREAK_ENABLED
  37
+//`define CFG_GDBSTUB_ENABLED
  38
+
  39
+function integer clog2;
  40
+  input integer value;
  41
+  begin
  42
+    value = value - 1;
  43
+    for (clog2 = 0; value > 0; clog2 = clog2 + 1)
  44
+      value = value >> 1;
  45
+  end
  46
+endfunction
  47
+
  48
+`define CLOG2 clog2
  49
+
  50
+`endif
6  verilog/lm32/lm32_dcache.v
@@ -112,14 +112,14 @@ parameter bytes_per_line = 16;                          // Number of bytes per c
112 112
 parameter base_address = 0;                             // Base address of cachable memory
113 113
 parameter limit = 0;                                    // Limit (highest address) of cachable memory
114 114
 
115  
-localparam addr_offset_width = $clog2(bytes_per_line)-2;
116  
-localparam addr_set_width = $clog2(sets);
  115
+localparam addr_offset_width = `CLOG2(bytes_per_line)-2;
  116
+localparam addr_set_width = `CLOG2(sets);
117 117
 localparam addr_offset_lsb = 2;
118 118
 localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
119 119
 localparam addr_set_lsb = (addr_offset_msb+1);
120 120
 localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
121 121
 localparam addr_tag_lsb = (addr_set_msb+1);
122  
-localparam addr_tag_msb = $clog2(`CFG_DCACHE_LIMIT-`CFG_DCACHE_BASE_ADDRESS);
  122
+localparam addr_tag_msb = `CLOG2(`CFG_DCACHE_LIMIT-`CFG_DCACHE_BASE_ADDRESS);
123 123
 localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
124 124
 
125 125
 /////////////////////////////////////////////////////
6  verilog/lm32/lm32_icache.v
@@ -119,14 +119,14 @@ parameter bytes_per_line = 16;                          // Number of bytes per c
119 119
 parameter base_address = 0;                             // Base address of cachable memory
120 120
 parameter limit = 0;                                    // Limit (highest address) of cachable memory
121 121
 
122  
-localparam addr_offset_width = $clog2(bytes_per_line)-2;
123  
-localparam addr_set_width = $clog2(sets);
  122
+localparam addr_offset_width = `CLOG2(bytes_per_line)-2;
  123
+localparam addr_set_width = `CLOG2(sets);
124 124
 localparam addr_offset_lsb = 2;
125 125
 localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
126 126
 localparam addr_set_lsb = (addr_offset_msb+1);
127 127
 localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
128 128
 localparam addr_tag_lsb = (addr_set_msb+1);
129  
-localparam addr_tag_msb = $clog2(`CFG_ICACHE_LIMIT-`CFG_ICACHE_BASE_ADDRESS);
  129
+localparam addr_tag_msb = `CLOG2(`CFG_ICACHE_LIMIT-`CFG_ICACHE_BASE_ADDRESS);
130 130
 localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
131 131
 
132 132
 /////////////////////////////////////////////////////
34  verilog/lm32/lm32_include.v
@@ -58,39 +58,7 @@
58 58
 // Common configuration options
59 59
 //
60 60
 
61  
-`define CFG_EBA_RESET 32'h00860000
62  
-`define CFG_DEBA_RESET 32'h10000000
63  
-
64  
-`define CFG_PL_MULTIPLY_ENABLED
65  
-`define CFG_PL_BARREL_SHIFT_ENABLED
66  
-`define CFG_SIGN_EXTEND_ENABLED
67  
-`define CFG_MC_DIVIDE_ENABLED
68  
-`define CFG_EBR_POSEDGE_REGISTER_FILE
69  
-
70  
-`define CFG_ICACHE_ENABLED
71  
-`define CFG_ICACHE_ASSOCIATIVITY   1
72  
-`define CFG_ICACHE_SETS            256
73  
-`define CFG_ICACHE_BYTES_PER_LINE  16
74  
-`define CFG_ICACHE_BASE_ADDRESS    32'h0
75  
-`define CFG_ICACHE_LIMIT           32'h7fffffff
76  
-
77  
-`define CFG_DCACHE_ENABLED
78  
-`define CFG_DCACHE_ASSOCIATIVITY   1
79  
-`define CFG_DCACHE_SETS            256
80  
-`define CFG_DCACHE_BYTES_PER_LINE  16
81  
-`define CFG_DCACHE_BASE_ADDRESS    32'h0
82  
-`define CFG_DCACHE_LIMIT           32'h7fffffff
83  
-
84  
-// Enable Debugging
85  
-//`define CFG_JTAG_ENABLED
86  
-//`define CFG_JTAG_UART_ENABLED
87  
-//`define CFG_DEBUG_ENABLED
88  
-//`define CFG_HW_DEBUG_ENABLED
89  
-//`define CFG_ROM_DEBUG_ENABLED
90  
-//`define CFG_BREAKPOINTS 32'h4
91  
-//`define CFG_WATCHPOINTS 32'h4
92  
-//`define CFG_EXTERNAL_BREAK_ENABLED
93  
-//`define CFG_GDBSTUB_ENABLED
  61
+`include "lm32_config.v"
94 62
 
95 63
 //
96 64
 // End of common configuration options
18  verilog/lm32/lm32_instruction_unit.v
@@ -179,7 +179,7 @@ parameter base_address = 0;                             // Base address of cacha
179 179
 parameter limit = 0;                                    // Limit (highest address) of cachable memory
180 180
 
181 181
 // For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used 
182  
-localparam addr_offset_width = bytes_per_line == 4 ? 1 : $clog2(bytes_per_line)-2;
  182
+localparam addr_offset_width = bytes_per_line == 4 ? 1 : `CLOG2(bytes_per_line)-2;
183 183
 localparam addr_offset_lsb = 2;
184 184
 localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
185 185
 
@@ -388,18 +388,18 @@ reg alternate_eba_taken;
388 388
        // ----- Parameters -------
389 389
        .pmi_family             (`LATTICE_FAMILY),
390 390
 	 
391  
-       //.pmi_addr_depth_a       (1 << $clog2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
392  
-       //.pmi_addr_width_a       ($clog2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
  391
+       //.pmi_addr_depth_a       (1 << `CLOG2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
  392
+       //.pmi_addr_width_a       (`CLOG2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
393 393
        //.pmi_data_width_a       (`LM32_WORD_WIDTH),
394  
-       //.pmi_addr_depth_b       (1 << $clog2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
395  
-       //.pmi_addr_width_b       ($clog2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
  394
+       //.pmi_addr_depth_b       (1 << `CLOG2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
  395
+       //.pmi_addr_width_b       (`CLOG2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
396 396
        //.pmi_data_width_b       (`LM32_WORD_WIDTH),
397 397
 	 
398 398
        .pmi_addr_depth_a       (`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1),
399  
-       .pmi_addr_width_a       ($clog2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
  399
+       .pmi_addr_width_a       (`CLOG2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
400 400
        .pmi_data_width_a       (`LM32_WORD_WIDTH),
401 401
        .pmi_addr_depth_b       (`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1),
402  
-       .pmi_addr_width_b       ($clog2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
  402
+       .pmi_addr_width_b       (`CLOG2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
403 403
        .pmi_data_width_b       (`LM32_WORD_WIDTH),
404 404
 	 
405 405
        .pmi_regmode_a          ("noreg"),
@@ -418,8 +418,8 @@ reg alternate_eba_taken;
418 418
 	    .ResetB                 (rst_i),
419 419
 	    .DataInA                ({32{1'b0}}),
420 420
 	    .DataInB                (irom_store_data_m),
421  
-	    .AddressA               (pc_a[$clog2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)+2-1:2]),
422  
-	    .AddressB               (irom_address_xm[$clog2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)+2-1:2]),
  421
+	    .AddressA               (pc_a[`CLOG2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)+2-1:2]),
  422
+	    .AddressB               (irom_address_xm[`CLOG2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)+2-1:2]),
423 423
 	    .ClockEnA               (!stall_a),
424 424
 	    .ClockEnB               (!stall_x || !stall_m),
425 425
 	    .WrA                    (`FALSE),
18  verilog/lm32/lm32_load_store_unit.v
@@ -139,7 +139,7 @@ parameter base_address = 0;                             // Base address of cacha
139 139
 parameter limit = 0;                                    // Limit (highest address) of cachable memory
140 140
 
141 141
 // For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used 
142  
-localparam addr_offset_width = bytes_per_line == 4 ? 1 : $clog2(bytes_per_line)-2;
  142
+localparam addr_offset_width = bytes_per_line == 4 ? 1 : `CLOG2(bytes_per_line)-2;
143 143
 localparam addr_offset_lsb = 2;
144 144
 localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
145 145
 
@@ -293,18 +293,18 @@ reg wb_load_complete;                                   // Indicates when a Wish
293 293
        // ----- Parameters -------
294 294
        .pmi_family             (`LATTICE_FAMILY),
295 295
 
296  
-       //.pmi_addr_depth_a       (1 << $clog2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
297  
-       //.pmi_addr_width_a       ($clog2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
  296
+       //.pmi_addr_depth_a       (1 << `CLOG2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
  297
+       //.pmi_addr_width_a       (`CLOG2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
298 298
        //.pmi_data_width_a       (`LM32_WORD_WIDTH),
299  
-       //.pmi_addr_depth_b       (1 << $clog2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
300  
-       //.pmi_addr_width_b       ($clog2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
  299
+       //.pmi_addr_depth_b       (1 << `CLOG2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
  300
+       //.pmi_addr_width_b       (`CLOG2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
301 301
        //.pmi_data_width_b       (`LM32_WORD_WIDTH),
302 302
 	
303 303
        .pmi_addr_depth_a       (`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1),
304  
-       .pmi_addr_width_a       ($clog2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
  304
+       .pmi_addr_width_a       (`CLOG2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
305 305
        .pmi_data_width_a       (`LM32_WORD_WIDTH),
306 306
        .pmi_addr_depth_b       (`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1),
307  
-       .pmi_addr_width_b       ($clog2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
  307
+       .pmi_addr_width_b       (`CLOG2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
308 308
        .pmi_data_width_b       (`LM32_WORD_WIDTH),
309 309
 
310 310
        .pmi_regmode_a          ("noreg"),
@@ -323,8 +323,8 @@ reg wb_load_complete;                                   // Indicates when a Wish
323 323
 	    .ResetB                 (rst_i),
324 324
 	    .DataInA                ({32{1'b0}}),
325 325
 	    .DataInB                (dram_store_data_m),
326  
-	    .AddressA               (load_store_address_x[$clog2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)+2-1:2]),
327  
-	    .AddressB               (load_store_address_m[$clog2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)+2-1:2]),
  326
+	    .AddressA               (load_store_address_x[`CLOG2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)+2-1:2]),
  327
+	    .AddressB               (load_store_address_m[`CLOG2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)+2-1:2]),
328 328
 	    // .ClockEnA               (!stall_x & (load_x | store_x)),
329 329
 	    .ClockEnA               (!stall_x),
330 330
 	    .ClockEnB               (!stall_m),

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