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  • 2 files changed
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Showing with 20 additions and 20 deletions.
  1. +6 −10 milkymist/framebuffer/__init__.py
  2. +14 −10 tb/framebuffer/framebuffer.py
16 milkymist/framebuffer/__init__.py
View
@@ -2,7 +2,7 @@
from migen.flow.actor import *
from migen.flow.network import *
from migen.flow import plumbing
-from migen.actorlib import ala, misc, dma_asmi, structuring, sim
+from migen.actorlib import misc, dma_asmi, structuring, sim
from migen.bank.description import *
from migen.bank import csrgen
@@ -136,9 +136,8 @@ def get_fragment(self):
If(hcounter == tp.hscan,
hcounter.eq(0),
If(vcounter == tp.vscan,
- vcounter.eq(0)
- # FIXME: work around Flow bug
- #self.endpoints["timing"].ack.eq(1)
+ vcounter.eq(0),
+ self.endpoints["timing"].ack.eq(1)
).Else(
vcounter.eq(vcounter + 1)
)
@@ -236,8 +235,7 @@ def __init__(self, address, asmiport, simulation=False):
packed_pixels = structuring.pack_layout(_pixel_layout, pack_factor)
fi = ActorNode(_FrameInitiator(asmi_bits, length_bits, alignment_bits))
- adrloop = ActorNode(misc.IntSequence(length_bits))
- adrbase = ActorNode(ala.Add(BV(asmi_bits)))
+ adrloop = ActorNode(misc.IntSequence(length_bits, asmi_bits))
adrbuffer = ActorNode(plumbing.Buffer)
#dma = ActorNode(dma_asmi.SequentialReader(asmiport))
dma = ActorNode(FakeDMA(asmiport))
@@ -250,10 +248,8 @@ def __init__(self, address, asmiport, simulation=False):
fifo = ActorNode(FIFO())
g = DataFlowGraph()
- g.add_connection(fi, adrloop, source_subr=["length"])
- g.add_connection(adrloop, adrbase, sink_subr=["a"])
- g.add_connection(fi, adrbase, source_subr=["base"], sink_subr=["b"])
- g.add_connection(adrbase, adrbuffer)
+ g.add_connection(fi, adrloop, source_subr=["length", "base"])
+ g.add_connection(adrloop, adrbuffer)
g.add_connection(adrbuffer, dma)
g.add_connection(dma, cast)
g.add_connection(cast, unpack)
24 tb/framebuffer/framebuffer.py
View
@@ -18,17 +18,21 @@ def main():
sim.run(1)
def csr_w(addr, d):
sim.wr(dut.bank.description[addr].field.storage, d)
- csr_w(1, 2) # hres
- csr_w(2, 3) # hsync_start
- csr_w(3, 4) # hsync_stop
- csr_w(4, 5) # hscan
- csr_w(5, 2) # vres
- csr_w(6, 3) # vsync_start
- csr_w(7, 4) # vsync_stop
- csr_w(8, 5) # vscan
- csr_w(10, 2*2*4) # length
+
+ hres = 4
+ vres = 4
+
+ csr_w(1, hres) # hres
+ csr_w(2, hres+3) # hsync_start
+ csr_w(3, hres+5) # hsync_stop
+ csr_w(4, hres+10) # hscan
+ csr_w(5, vres) # vres
+ csr_w(6, vres+3) # vsync_start
+ csr_w(7, vres+5) # vsync_stop
+ csr_w(8, vres+10) # vscan
+ csr_w(10, hres*vres*4) # length
csr_w(0, 1) # enable
- sim.run(200)
+ sim.run(1000)
main()

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