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16  milkymist/framebuffer/__init__.py
@@ -2,7 +2,7 @@
2 2
 from migen.flow.actor import *
3 3
 from migen.flow.network import *
4 4
 from migen.flow import plumbing
5  
-from migen.actorlib import ala, misc, dma_asmi, structuring, sim
  5
+from migen.actorlib import misc, dma_asmi, structuring, sim
6 6
 from migen.bank.description import *
7 7
 from migen.bank import csrgen
8 8
 
@@ -136,9 +136,8 @@ def get_fragment(self):
136 136
 				If(hcounter == tp.hscan,
137 137
 					hcounter.eq(0),
138 138
 					If(vcounter == tp.vscan,
139  
-						vcounter.eq(0)
140  
-						# FIXME: work around Flow bug
141  
-						#self.endpoints["timing"].ack.eq(1)
  139
+						vcounter.eq(0),
  140
+						self.endpoints["timing"].ack.eq(1)
142 141
 					).Else(
143 142
 						vcounter.eq(vcounter + 1)
144 143
 					)
@@ -236,8 +235,7 @@ def __init__(self, address, asmiport, simulation=False):
236 235
 		packed_pixels = structuring.pack_layout(_pixel_layout, pack_factor)
237 236
 		
238 237
 		fi = ActorNode(_FrameInitiator(asmi_bits, length_bits, alignment_bits))
239  
-		adrloop = ActorNode(misc.IntSequence(length_bits))
240  
-		adrbase = ActorNode(ala.Add(BV(asmi_bits)))
  238
+		adrloop = ActorNode(misc.IntSequence(length_bits, asmi_bits))
241 239
 		adrbuffer = ActorNode(plumbing.Buffer)
242 240
 		#dma = ActorNode(dma_asmi.SequentialReader(asmiport))
243 241
 		dma = ActorNode(FakeDMA(asmiport))
@@ -250,10 +248,8 @@ def __init__(self, address, asmiport, simulation=False):
250 248
 			fifo = ActorNode(FIFO())
251 249
 		
252 250
 		g = DataFlowGraph()
253  
-		g.add_connection(fi, adrloop, source_subr=["length"])
254  
-		g.add_connection(adrloop, adrbase, sink_subr=["a"])
255  
-		g.add_connection(fi, adrbase, source_subr=["base"], sink_subr=["b"])
256  
-		g.add_connection(adrbase, adrbuffer)
  251
+		g.add_connection(fi, adrloop, source_subr=["length", "base"])
  252
+		g.add_connection(adrloop, adrbuffer)
257 253
 		g.add_connection(adrbuffer, dma)
258 254
 		g.add_connection(dma, cast)
259 255
 		g.add_connection(cast, unpack)
24  tb/framebuffer/framebuffer.py
@@ -18,17 +18,21 @@ def main():
18 18
 	sim.run(1)
19 19
 	def csr_w(addr, d):
20 20
 		sim.wr(dut.bank.description[addr].field.storage, d)
21  
-	csr_w(1, 2) # hres
22  
-	csr_w(2, 3) # hsync_start
23  
-	csr_w(3, 4) # hsync_stop
24  
-	csr_w(4, 5) # hscan
25  
-	csr_w(5, 2) # vres
26  
-	csr_w(6, 3) # vsync_start
27  
-	csr_w(7, 4) # vsync_stop
28  
-	csr_w(8, 5) # vscan
29  
-	csr_w(10, 2*2*4) # length
  21
+		
  22
+	hres = 4
  23
+	vres = 4
  24
+	
  25
+	csr_w(1, hres) # hres
  26
+	csr_w(2, hres+3) # hsync_start
  27
+	csr_w(3, hres+5) # hsync_stop
  28
+	csr_w(4, hres+10) # hscan
  29
+	csr_w(5, vres) # vres
  30
+	csr_w(6, vres+3) # vsync_start
  31
+	csr_w(7, vres+5) # vsync_stop
  32
+	csr_w(8, vres+10) # vscan
  33
+	csr_w(10, hres*vres*4) # length
30 34
 	csr_w(0, 1) # enable
31 35
 	
32  
-	sim.run(200)
  36
+	sim.run(1000)
33 37
 
34 38
 main()

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