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Showing 2 changed files with 17 additions and 16 deletions. Show diff stats Hide diff stats

  1. 23  build.py
  2. 10  soc.xst
23  build.py
@@ -15,35 +15,46 @@ def main():
15 15
 	platform.add_platform_command("""
16 16
 NET "{clk50}" TNM_NET = "GRPclk50";
17 17
 TIMESPEC "TSclk50" = PERIOD "GRPclk50" 20 ns HIGH 50%;
  18
+""", clk50=platform.lookup_request("clk50"))
  19
+
  20
+	platform.add_platform_command("""
18 21
 INST "m1crg/wr_bufpll" LOC = "BUFPLL_X0Y2";
19 22
 INST "m1crg/rd_bufpll" LOC = "BUFPLL_X0Y3";
20 23
 
21 24
 PIN "m1crg/bufg_x1.O" CLOCK_DEDICATED_ROUTE = FALSE;
  25
+""")
22 26
 
  27
+	if hasattr(soc, "fb"):
  28
+		platform.add_platform_command("""
23 29
 NET "vga_clk" TNM_NET = "GRPvga_clk";
24 30
 NET "sys_clk" TNM_NET = "GRPsys_clk";
25 31
 TIMESPEC "TSise_sucks1" = FROM "GRPvga_clk" TO "GRPsys_clk" TIG;
26 32
 TIMESPEC "TSise_sucks2" = FROM "GRPsys_clk" TO "GRPvga_clk" TIG;
  33
+""")
27 34
 
  35
+	if hasattr(soc, "minimac"):
  36
+		platform.add_platform_command("""
28 37
 NET "{phy_rx_clk}" TNM_NET = "GRPphy_rx_clk";
29 38
 NET "{phy_tx_clk}" TNM_NET = "GRPphy_tx_clk";
30 39
 TIMESPEC "TSphy_rx_clk" = PERIOD "GRPphy_rx_clk" 40 ns HIGH 50%;
31 40
 TIMESPEC "TSphy_tx_clk" = PERIOD "GRPphy_tx_clk" 40 ns HIGH 50%;
32 41
 TIMESPEC "TSphy_tx_clk_io" = FROM "GRPphy_tx_clk" TO "PADS" 10 ns;
33 42
 TIMESPEC "TSphy_rx_clk_io" = FROM "PADS" TO "GRPphy_rx_clk" 10 ns;
  43
+""",
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+		phy_rx_clk=platform.lookup_request("eth_clocks").rx,
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+		phy_tx_clk=platform.lookup_request("eth_clocks").tx,)
34 46
 
  47
+	if hasattr(soc, "dvisampler0"):
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+		platform.add_platform_command("""
35 49
 NET "{dviclk0}" TNM_NET = "GRPdviclk0";
36 50
 NET "{dviclk0}" CLOCK_DEDICATED_ROUTE = FALSE;
37 51
 TIMESPEC "TSdviclk0" = PERIOD "GRPdviclk0" 26.7 ns HIGH 50%;
  52
+""", dviclk0=platform.lookup_request("dvi_in", 0).clk)
  53
+		platform.add_platform_command("""
38 54
 NET "{dviclk1}" TNM_NET = "GRPdviclk1";
39 55
 NET "{dviclk1}" CLOCK_DEDICATED_ROUTE = FALSE;
40 56
 TIMESPEC "TSdviclk1" = PERIOD "GRPdviclk1" 26.7 ns HIGH 50%;
41  
-""",
42  
-		clk50=platform.lookup_request("clk50"),
43  
-		phy_rx_clk=platform.lookup_request("eth_clocks").rx,
44  
-		phy_tx_clk=platform.lookup_request("eth_clocks").tx,
45  
-		dviclk0=platform.lookup_request("dvi_in", 0).clk,
46  
-		dviclk1=platform.lookup_request("dvi_in", 1).clk)
  57
+""", dviclk1=platform.lookup_request("dvi_in", 1).clk)
47 58
 	
48 59
 	for d in ["m1crg", "s6ddrphy", "minimac3"]:
49 60
 		platform.add_source_dir(os.path.join("verilog", d))
10  soc.xst
... ...
@@ -1,10 +0,0 @@
1  
-run
2  
--ifn soc.prj
3  
--top soc
4  
--ifmt MIXED
5  
--opt_mode SPEED
6  
--opt_level 2
7  
--resource_sharing no
8  
--reduce_control_sets auto
9  
--ofn soc.ngc
10  
--p xc6slx45-fgg484-2

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