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8  software/bios/ddrinit.c
@@ -61,6 +61,7 @@ static void init_sequence(void)
61 61
 	
62 62
 	/* Load Mode Register */
63 63
 	setaddr(0x0132); /* Reset DLL, CL=3, BL=4 */
  64
+	//setaddr(0x0162); /* Reset DLL, CL=2.5, BL=4 */
64 65
 	CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS;
65 66
 	cdelay(200);
66 67
 	
@@ -77,6 +78,7 @@ static void init_sequence(void)
77 78
 	
78 79
 	/* Load Mode Register */
79 80
 	setaddr(0x0032); /* CL=3, BL=4 */
  81
+	//setaddr(0x0062); /* CL=2.5, BL=4 */
80 82
 	CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS;
81 83
 	cdelay(200);
82 84
 }
@@ -103,9 +105,9 @@ void ddrrd(char *startaddr)
103 105
 	cdelay(15);
104 106
 	
105 107
 	for(i=0;i<8;i++)
106  
-		printf("%08x ", MMPTR(0xe0000834+4*i));
  108
+		printf("%02x", MMPTR(0xe0000834+4*i));
107 109
 	for(i=0;i<8;i++)
108  
-		printf("%08x ", MMPTR(0xe0000884+4*i));
  110
+		printf("%02x", MMPTR(0xe0000884+4*i));
109 111
 	printf("\n");
110 112
 }
111 113
 
@@ -127,7 +129,7 @@ void ddrwr(char *startaddr)
127 129
 	
128 130
 	for(i=0;i<8;i++) {
129 131
 		MMPTR(0xe0000814+4*i) = i;
130  
-		MMPTR(0xe0000864+4*i) = i;
  132
+		MMPTR(0xe0000864+4*i) = 0xf0 + i;
131 133
 	}
132 134
 	
133 135
 	setaddr(addr);
96  verilog/s6ddrphy/s6ddrphy.v
@@ -14,25 +14,8 @@
14 14
  * This PHY only supports CAS Latency 3.
15 15
  * Read commands must be sent on phase 0.
16 16
  * Write commands must be sent on phase 1.
17  
- *
18  
- ************* DETAILED TIMING ************
19  
- * Command path:
20  
- *   posedge sys_clk             + 1
21  
- *   posedge clk2x_270           + 0.375
22  
- *   negedge clk2x_270           + 0.125
23  
- * Command latency:              1.5 cycles
24  
- *
25  
- * Data write path (phase 0, word 0):
26  
- *   posedge sys_clk [oserdes]   + 1
27  
- *   strobe [oserdes]            + 1
28  
- * Data write latency:           2 cycles
29  
- *
30  
- * DQS OE path:
31  
- *   posedge sys_clk             + 1
32  
- *   posedge clk2x_270           + 0.375
33  
- *   negedge clk2x_270 [oddr]    + 0.125
34  
- * DQS OE latency                1.5 cycles
35 17
  */
  18
+
36 19
 module s6ddrphy #(
37 20
 	parameter NUM_AD = 0,
38 21
 	parameter NUM_BA = 0,
@@ -128,7 +111,7 @@ ODDR2 #(
128 111
  */
129 112
 
130 113
 reg phase_sel;
131  
-always @(negedge clk2x_270)
  114
+always @(posedge clk2x_270)
132 115
 	phase_sel <= sys_clk;
133 116
 
134 117
 reg [NUM_AD-1:0] r_dfi_address_p0;
@@ -146,7 +129,7 @@ reg r_dfi_ras_n_p1;
146 129
 reg r_dfi_cas_n_p1;
147 130
 reg r_dfi_we_n_p1;
148 131
 	
149  
-always @(posedge sys_clk) begin
  132
+always @(posedge clk2x_270) begin
150 133
 	r_dfi_address_p0 <= dfi_address_p0;
151 134
 	r_dfi_bank_p0 <= dfi_bank_p0;
152 135
 	r_dfi_cs_n_p0 <= dfi_cs_n_p0;
@@ -164,56 +147,23 @@ always @(posedge sys_clk) begin
164 147
 	r_dfi_we_n_p1 <= dfi_we_n_p1;
165 148
 end
166 149
 
167  
-reg [NUM_AD-1:0] r2_dfi_address_p0;
168  
-reg [NUM_BA-1:0] r2_dfi_bank_p0;
169  
-reg r2_dfi_cs_n_p0;
170  
-reg r2_dfi_cke_p0;
171  
-reg r2_dfi_ras_n_p0;
172  
-reg r2_dfi_cas_n_p0;
173  
-reg r2_dfi_we_n_p0;
174  
-reg [NUM_AD-1:0] r2_dfi_address_p1;
175  
-reg [NUM_BA-1:0] r2_dfi_bank_p1;
176  
-reg r2_dfi_cs_n_p1;
177  
-reg r2_dfi_cke_p1;
178  
-reg r2_dfi_ras_n_p1;
179  
-reg r2_dfi_cas_n_p1;
180  
-reg r2_dfi_we_n_p1;
181  
-	
182 150
 always @(posedge clk2x_270) begin
183  
-	r2_dfi_address_p0 <= r_dfi_address_p0;
184  
-	r2_dfi_bank_p0 <= r_dfi_bank_p0;
185  
-	r2_dfi_cs_n_p0 <= r_dfi_cs_n_p0;
186  
-	r2_dfi_cke_p0 <= r_dfi_cke_p0;
187  
-	r2_dfi_ras_n_p0 <= r_dfi_ras_n_p0;
188  
-	r2_dfi_cas_n_p0 <= r_dfi_cas_n_p0;
189  
-	r2_dfi_we_n_p0 <= r_dfi_we_n_p0;
190  
-	
191  
-	r2_dfi_address_p1 <= r_dfi_address_p1;
192  
-	r2_dfi_bank_p1 <= r_dfi_bank_p1;
193  
-	r2_dfi_cs_n_p1 <= r_dfi_cs_n_p1;
194  
-	r2_dfi_cke_p1 <= r_dfi_cke_p1;
195  
-	r2_dfi_ras_n_p1 <= r_dfi_ras_n_p1;
196  
-	r2_dfi_cas_n_p1 <= r_dfi_cas_n_p1;
197  
-	r2_dfi_we_n_p1 <= r_dfi_we_n_p1;
198  
-end
199  
-
200  
-always @(negedge clk2x_270) begin
201 151
 	if(phase_sel) begin
202  
-		sd_a <= r2_dfi_address_p0;
203  
-		sd_ba <= r2_dfi_bank_p0;
204  
-		sd_cs_n <= r2_dfi_cs_n_p0;
205  
-		sd_cke <= r2_dfi_cke_p0;
206  
-		sd_ras_n <= r2_dfi_ras_n_p0;
207  
-		sd_cas_n <= r2_dfi_cas_n_p0;
208  
-		sd_we_n <= r2_dfi_we_n_p0;
  152
+		sd_a <= r_dfi_address_p0;
  153
+		sd_ba <= r_dfi_bank_p0;
  154
+		sd_cs_n <= r_dfi_cs_n_p0;
  155
+		sd_cke <= r_dfi_cke_p0;
  156
+		sd_ras_n <= r_dfi_ras_n_p0;
  157
+		sd_cas_n <= r_dfi_cas_n_p0;
  158
+		sd_we_n <= r_dfi_we_n_p0;
209 159
 	end else begin
210  
-		sd_a <= r2_dfi_address_p1;
211  
-		sd_ba <= r2_dfi_bank_p1;
212  
-		sd_cs_n <= r2_dfi_cs_n_p1;
213  
-		sd_cke <= r2_dfi_cke_p1;
214  
-		sd_ras_n <= r2_dfi_ras_n_p1;
215  
-		sd_cas_n <= r2_dfi_cas_n_p1;
216  
-		sd_we_n <= r2_dfi_we_n_p1;
  160
+		sd_a <= r_dfi_address_p1;
  161
+		sd_ba <= r_dfi_bank_p1;
  162
+		sd_cs_n <= r_dfi_cs_n_p1;
  163
+		sd_cke <= r_dfi_cke_p1;
  164
+		sd_ras_n <= r_dfi_ras_n_p1;
  165
+		sd_cas_n <= r_dfi_cas_n_p1;
  166
+		sd_we_n <= r_dfi_we_n_p1;
217 167
 	end
218 168
 end
219 169
 
@@ -390,15 +340,15 @@ endgenerate
390 340
  * DQ/DQS/DM control
391 341
  */
392 342
 
393  
-reg r_dfi_wrdata_en_p1;
394  
-always @(posedge sys_clk)
395  
-	r_dfi_wrdata_en_p1 <= dfi_wrdata_en_p1;
  343
+reg r_dfi_wrdata_en;
  344
+always @(posedge clk2x_270)
  345
+	r_dfi_wrdata_en <= dfi_wrdata_en_p1;
396 346
 
397  
-reg r2_dfi_wrdata_en_p1;
  347
+reg r2_dfi_wrdata_en;
398 348
 always @(posedge clk2x_270)
399  
-	r2_dfi_wrdata_en_p1 <= r_dfi_wrdata_en_p1;
  349
+	r2_dfi_wrdata_en <= r_dfi_wrdata_en;
400 350
 
401  
-assign drive_dqs = r2_dfi_wrdata_en_p1;
  351
+assign drive_dqs = r2_dfi_wrdata_en;
402 352
 assign drive_dq = dfi_wrdata_en_p1;
403 353
 
404 354
 wire rddata_valid;

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