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  • 8 files changed
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8  milkymist/dvisampler/__init__.py
@@ -8,6 +8,7 @@
8 8
 from milkymist.dvisampler.charsync import CharSync
9 9
 from milkymist.dvisampler.decoding import Decoding
10 10
 from milkymist.dvisampler.chansync import ChanSync
  11
+from milkymist.dvisampler.resdetection import ResolutionDetection
11 12
 
12 13
 class DVISampler(Module, AutoReg):
13 14
 	def __init__(self, inversions=""):
@@ -59,3 +60,10 @@ def __init__(self, inversions=""):
59 60
 		b = self.chansync.data_out0.d
60 61
 		hsync = self.chansync.data_out0.c[0]
61 62
 		vsync = self.chansync.data_out0.c[1]
  63
+
  64
+		self.submodules.resdetection = ResolutionDetection()
  65
+		self.comb += [
  66
+			self.resdetection.de.eq(de),
  67
+			self.resdetection.hsync.eq(hsync),
  68
+			self.resdetection.vsync.eq(vsync)
  69
+		]
3  milkymist/dvisampler/charsync.py
@@ -13,6 +13,7 @@ def __init__(self, required_controls=8):
13 13
 		self.data = Signal(10)
14 14
 
15 15
 		self._r_char_synced = RegisterField(1, READ_ONLY, WRITE_ONLY)
  16
+		self._r_ctl_pos = RegisterField(bits_for(9), READ_ONLY, WRITE_ONLY)
16 17
 
17 18
 		###
18 19
 
@@ -23,6 +24,7 @@ def __init__(self, required_controls=8):
23 24
 
24 25
 		found_control = Signal()
25 26
 		control_position = Signal(max=10)
  27
+		self.sync.pix += found_control.eq(0)
26 28
 		for i in range(10):
27 29
 			self.sync.pix += If(optree("|", [raw[i:i+10] == t for t in control_tokens]),
28 30
 			  	found_control.eq(1),
@@ -47,5 +49,6 @@ def __init__(self, required_controls=8):
47 49
 			previous_control_position.eq(control_position)
48 50
 		]
49 51
 		self.specials += MultiReg(self.synced, self._r_char_synced.field.w)
  52
+		self.specials += MultiReg(word_sel, self._r_ctl_pos.field.w)
50 53
 
51 54
 		self.sync.pix += self.data.eq(raw >> word_sel)
5  milkymist/dvisampler/decoding.py
@@ -13,7 +13,10 @@ def __init__(self):
13 13
 
14 14
 		###
15 15
 
16  
-		self.sync.pix += self.output.de.eq(1)
  16
+		self.sync.pix += [
  17
+			self.output.de.eq(1),
  18
+			self.output.c.eq(0)
  19
+		]
17 20
 		for i, t in enumerate(control_tokens):
18 21
 			self.sync.pix += If(self.input == t,
19 22
 				self.output.de.eq(0),
16  milkymist/dvisampler/edid.py
@@ -7,14 +7,14 @@
7 7
 from migen.bank.description import AutoReg
8 8
 
9 9
 _default_edid = [
10  
-	0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x3D, 0x17, 0x20, 0x11, 0x3E, 0x11, 0x00, 0x00,
11  
-	0x01, 0x17, 0x01, 0x03, 0x80, 0x30, 0x1B, 0x78, 0x08, 0x1D, 0xC5, 0xA4, 0x55, 0x54, 0xA0, 0x27,
12  
-	0x0C, 0x50, 0x54, 0x3F, 0xC0, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
13  
-	0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x88, 0x13, 0x20, 0x3C, 0x30, 0x58, 0x2D, 0x20, 0x58, 0x2C,
14  
-	0x45, 0x00, 0xE0, 0x0E, 0x11, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x4D, 0x31, 0x20,
15  
-	0x44, 0x56, 0x49, 0x20, 0x6D, 0x69, 0x78, 0x65, 0x72, 0x0A, 0x00, 0x00, 0x00, 0x10, 0x00, 0x32,
16  
-	0x4C, 0x1E, 0x53, 0x11, 0x00, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0x10,
17  
-	0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x00, 0x2C,
  10
+	0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x3D, 0x17, 0x32, 0x12, 0x2A, 0x6A, 0xBF, 0x00,
  11
+	0x05, 0x17, 0x01, 0x03, 0x80, 0x28, 0x1E, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  12
+	0x00, 0x00, 0x00, 0x2E, 0x00, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
  13
+	0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0xE2, 0x0E, 0x20, 0x20, 0x31, 0x58, 0x13, 0x20, 0x20, 0x80,
  14
+	0x14, 0x00, 0x28, 0x1E, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x4D, 0x31, 0x20,
  15
+	0x44, 0x56, 0x49, 0x20, 0x6D, 0x69, 0x78, 0x65, 0x72, 0x0A, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,
  16
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
  17
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF,
18 18
 ]
19 19
 
20 20
 class EDID(Module, AutoReg):
71  milkymist/dvisampler/resdetection.py
... ...
@@ -0,0 +1,71 @@
  1
+from migen.fhdl.structure import *
  2
+from migen.fhdl.module import Module
  3
+from migen.genlib.cdc import MultiReg
  4
+from migen.bank.description import *
  5
+
  6
+class ResolutionDetection(Module, AutoReg):
  7
+	def __init__(self, nbits=10):
  8
+		self.hsync = Signal()
  9
+		self.vsync = Signal()
  10
+		self.de = Signal()
  11
+
  12
+		self._hres = RegisterField(nbits, READ_ONLY, WRITE_ONLY)
  13
+		self._vres = RegisterField(nbits, READ_ONLY, WRITE_ONLY)
  14
+		self._de_cycles = RegisterField(2*nbits, READ_ONLY, WRITE_ONLY)
  15
+
  16
+		###
  17
+
  18
+		# HRES/VRES
  19
+		hsync_r = Signal()
  20
+		vsync_r = Signal()
  21
+		p_hsync = Signal()
  22
+		p_vsync = Signal()
  23
+		self.sync.pix += [
  24
+			hsync_r.eq(self.hsync),
  25
+			vsync_r.eq(self.vsync),
  26
+		]
  27
+		self.comb += [
  28
+			p_hsync.eq(self.hsync & ~hsync_r),
  29
+			p_vsync.eq(self.vsync & ~vsync_r)
  30
+		]
  31
+
  32
+		hcounter = Signal(nbits)
  33
+		vcounter = Signal(nbits)
  34
+		self.sync.pix += [
  35
+			If(p_hsync,
  36
+				hcounter.eq(0)
  37
+			).Elif(self.de,
  38
+				hcounter.eq(hcounter + 1)
  39
+			),
  40
+			If(p_vsync,
  41
+				vcounter.eq(0)
  42
+			).Elif(p_hsync,
  43
+				vcounter.eq(vcounter + 1)
  44
+			)
  45
+		]
  46
+
  47
+		hcounter_st = Signal(nbits)
  48
+		vcounter_st = Signal(nbits)
  49
+		self.sync.pix += [
  50
+			If(p_hsync & (hcounter != 0), hcounter_st.eq(hcounter)),
  51
+			If(p_vsync & (vcounter != 0), vcounter_st.eq(vcounter))
  52
+		]
  53
+		self.specials += MultiReg(hcounter_st, self._hres.field.w)
  54
+		self.specials += MultiReg(vcounter_st, self._vres.field.w)
  55
+
  56
+		# DE
  57
+		de_r = Signal()
  58
+		pn_de = Signal()
  59
+		self.sync.pix += de_r.eq(self.de)
  60
+		self.comb += pn_de.eq(~self.de & de_r)
  61
+
  62
+		decounter = Signal(2*nbits)
  63
+		self.sync.pix += If(self.de,
  64
+				decounter.eq(decounter + 1)
  65
+			).Else(
  66
+				decounter.eq(0)
  67
+			)
  68
+
  69
+		decounter_st = Signal(2*nbits)
  70
+		self.sync.pix += If(pn_de, decounter_st.eq(decounter))
  71
+		self.specials += MultiReg(decounter_st, self._de_cycles.field.w)
4  software/include/base/stddef.h
... ...
@@ -1,7 +1,11 @@
1 1
 #ifndef __STDDEF_H
2 2
 #define __STDDEF_H
3 3
 
  4
+#ifdef __cplusplus
  5
+#define NULL 0
  6
+#else
4 7
 #define NULL ((void *)0)
  8
+#endif
5 9
 
6 10
 typedef unsigned long size_t;
7 11
 typedef long ptrdiff_t;
39  software/include/hw/dvisampler.h
@@ -14,20 +14,31 @@
14 14
 #define CSR_DVISAMPLER0_D0_PHASE	DVISAMPLER0_CSR(0x10)
15 15
 #define CSR_DVISAMPLER0_D0_PHASE_RESET	DVISAMPLER0_CSR(0x14)
16 16
 #define CSR_DVISAMPLER0_D0_CHAR_SYNCED	DVISAMPLER0_CSR(0x18)
17  
-
18  
-#define CSR_DVISAMPLER0_D1_DELAY_CTL	DVISAMPLER0_CSR(0x1C)
19  
-#define CSR_DVISAMPLER0_D1_DELAY_BUSY	DVISAMPLER0_CSR(0x20)
20  
-#define CSR_DVISAMPLER0_D1_PHASE	DVISAMPLER0_CSR(0x24)
21  
-#define CSR_DVISAMPLER0_D1_PHASE_RESET	DVISAMPLER0_CSR(0x28)
22  
-#define CSR_DVISAMPLER0_D1_CHAR_SYNCED	DVISAMPLER0_CSR(0x2C)
23  
-
24  
-#define CSR_DVISAMPLER0_D2_DELAY_CTL	DVISAMPLER0_CSR(0x30)
25  
-#define CSR_DVISAMPLER0_D2_DELAY_BUSY	DVISAMPLER0_CSR(0x34)
26  
-#define CSR_DVISAMPLER0_D2_PHASE	DVISAMPLER0_CSR(0x38)
27  
-#define CSR_DVISAMPLER0_D2_PHASE_RESET	DVISAMPLER0_CSR(0x3C)
28  
-#define CSR_DVISAMPLER0_D2_CHAR_SYNCED	DVISAMPLER0_CSR(0x40)
29  
-
30  
-#define CSR_DVISAMPLER0_CHAN_SYNCED	DVISAMPLER0_CSR(0x44)
  17
+#define CSR_DVISAMPLER0_D0_CTL_POS	DVISAMPLER0_CSR(0x1C)
  18
+
  19
+#define CSR_DVISAMPLER0_D1_DELAY_CTL	DVISAMPLER0_CSR(0x20)
  20
+#define CSR_DVISAMPLER0_D1_DELAY_BUSY	DVISAMPLER0_CSR(0x24)
  21
+#define CSR_DVISAMPLER0_D1_PHASE	DVISAMPLER0_CSR(0x28)
  22
+#define CSR_DVISAMPLER0_D1_PHASE_RESET	DVISAMPLER0_CSR(0x2C)
  23
+#define CSR_DVISAMPLER0_D1_CHAR_SYNCED	DVISAMPLER0_CSR(0x30)
  24
+#define CSR_DVISAMPLER0_D1_CTL_POS	DVISAMPLER0_CSR(0x34)
  25
+
  26
+#define CSR_DVISAMPLER0_D2_DELAY_CTL	DVISAMPLER0_CSR(0x38)
  27
+#define CSR_DVISAMPLER0_D2_DELAY_BUSY	DVISAMPLER0_CSR(0x3C)
  28
+#define CSR_DVISAMPLER0_D2_PHASE	DVISAMPLER0_CSR(0x40)
  29
+#define CSR_DVISAMPLER0_D2_PHASE_RESET	DVISAMPLER0_CSR(0x44)
  30
+#define CSR_DVISAMPLER0_D2_CHAR_SYNCED	DVISAMPLER0_CSR(0x48)
  31
+#define CSR_DVISAMPLER0_D2_CTL_POS	DVISAMPLER0_CSR(0x4C)
  32
+
  33
+#define CSR_DVISAMPLER0_CHAN_SYNCED	DVISAMPLER0_CSR(0x50)
  34
+
  35
+#define CSR_DVISAMPLER0_HRESH		DVISAMPLER0_CSR(0x54)
  36
+#define CSR_DVISAMPLER0_HRESL		DVISAMPLER0_CSR(0x58)
  37
+#define CSR_DVISAMPLER0_VRESH		DVISAMPLER0_CSR(0x5C)
  38
+#define CSR_DVISAMPLER0_VRESL		DVISAMPLER0_CSR(0x60)
  39
+#define CSR_DVISAMPLER0_DECNT2		DVISAMPLER0_CSR(0x64)
  40
+#define CSR_DVISAMPLER0_DECNT1		DVISAMPLER0_CSR(0x68)
  41
+#define CSR_DVISAMPLER0_DECNT0		DVISAMPLER0_CSR(0x6C)
31 42
 
32 43
 #define DVISAMPLER_DELAY_CAL		0x01
33 44
 #define DVISAMPLER_DELAY_RST		0x02
50  software/videomixer/main.c
... ...
@@ -1,4 +1,5 @@
1 1
 #include <stdio.h>
  2
+#include <stdlib.h>
2 3
 
3 4
 #include <irq.h>
4 5
 #include <uart.h>
@@ -6,6 +7,21 @@
6 7
 
7 8
 static int d0, d1, d2;
8 9
 
  10
+static void print_status(void)
  11
+{
  12
+	printf("Ph: %4d %4d %4d // %d%d%d [%d %d %d] // %d // %dx%d // %d\n", d0, d1, d2,
  13
+		CSR_DVISAMPLER0_D0_CHAR_SYNCED,
  14
+		CSR_DVISAMPLER0_D1_CHAR_SYNCED,
  15
+		CSR_DVISAMPLER0_D2_CHAR_SYNCED,
  16
+		CSR_DVISAMPLER0_D0_CTL_POS,
  17
+		CSR_DVISAMPLER0_D1_CTL_POS,
  18
+		CSR_DVISAMPLER0_D2_CTL_POS,
  19
+		CSR_DVISAMPLER0_CHAN_SYNCED,
  20
+		(CSR_DVISAMPLER0_HRESH << 8) | CSR_DVISAMPLER0_HRESL,
  21
+		(CSR_DVISAMPLER0_VRESH << 8) | CSR_DVISAMPLER0_VRESL,
  22
+		(CSR_DVISAMPLER0_DECNT2 << 16) | (CSR_DVISAMPLER0_DECNT1 << 8) |  CSR_DVISAMPLER0_DECNT0);
  23
+}
  24
+
9 25
 static void calibrate_delays(void)
10 26
 {
11 27
 	CSR_DVISAMPLER0_D0_DELAY_CTL = DVISAMPLER_DELAY_CAL;
@@ -60,28 +76,46 @@ static void adjust_phase(void)
60 76
 			CSR_DVISAMPLER0_D2_PHASE_RESET = 1;
61 77
 			break;
62 78
 	}
63  
-	printf("Ph: %4d %4d %4d // %d%d%d // %d\n", d0, d1, d2,
64  
-		CSR_DVISAMPLER0_D0_CHAR_SYNCED,
65  
-		CSR_DVISAMPLER0_D1_CHAR_SYNCED,
66  
-		CSR_DVISAMPLER0_D2_CHAR_SYNCED,
67  
-		CSR_DVISAMPLER0_CHAN_SYNCED);
  79
+}
  80
+
  81
+static int init_phase(void)
  82
+{
  83
+	int od0, od1, od2; 
  84
+	int i, j;
  85
+
  86
+	for(i=0;i<100;i++) {
  87
+		od0 = d0;
  88
+		od1 = d1;
  89
+		od2 = d2;
  90
+		for(j=0;j<1000;j++)
  91
+			adjust_phase();
  92
+		if((abs(d0 - od0) < 4) && (abs(d1 - od1) < 4) && (abs(d2 - od2) < 4))
  93
+			return 1;
  94
+	}
  95
+	return 0;
68 96
 }
69 97
 
70 98
 static void vmix(void)
71 99
 {
  100
+	int i;
72 101
 	unsigned int counter;
73 102
 
74 103
 	while(1) {
75 104
 		while(!CSR_DVISAMPLER0_PLL_LOCKED);
76 105
 		printf("PLL locked\n");
77 106
 		calibrate_delays();
78  
-		adjust_phase();
  107
+		if(init_phase())
  108
+			printf("Phase init OK\n");
  109
+		else
  110
+			printf("Phase did not settle\n");
  111
+		print_status();
79 112
 
80 113
 		counter = 0;
81 114
 		while(CSR_DVISAMPLER0_PLL_LOCKED) {
82 115
 			counter++;
83  
-			if(counter == 200000) {
84  
-				adjust_phase();
  116
+			if(counter == 2000000) {
  117
+				print_status();
  118
+				//adjust_phase();
85 119
 				counter = 0;
86 120
 			}
87 121
 		}

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