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8 milkymist/dvisampler/__init__.py
View
@@ -8,6 +8,7 @@
from milkymist.dvisampler.charsync import CharSync
from milkymist.dvisampler.decoding import Decoding
from milkymist.dvisampler.chansync import ChanSync
+from milkymist.dvisampler.resdetection import ResolutionDetection
class DVISampler(Module, AutoReg):
def __init__(self, inversions=""):
@@ -59,3 +60,10 @@ def __init__(self, inversions=""):
b = self.chansync.data_out0.d
hsync = self.chansync.data_out0.c[0]
vsync = self.chansync.data_out0.c[1]
+
+ self.submodules.resdetection = ResolutionDetection()
+ self.comb += [
+ self.resdetection.de.eq(de),
+ self.resdetection.hsync.eq(hsync),
+ self.resdetection.vsync.eq(vsync)
+ ]
3  milkymist/dvisampler/charsync.py
View
@@ -13,6 +13,7 @@ def __init__(self, required_controls=8):
self.data = Signal(10)
self._r_char_synced = RegisterField(1, READ_ONLY, WRITE_ONLY)
+ self._r_ctl_pos = RegisterField(bits_for(9), READ_ONLY, WRITE_ONLY)
###
@@ -23,6 +24,7 @@ def __init__(self, required_controls=8):
found_control = Signal()
control_position = Signal(max=10)
+ self.sync.pix += found_control.eq(0)
for i in range(10):
self.sync.pix += If(optree("|", [raw[i:i+10] == t for t in control_tokens]),
found_control.eq(1),
@@ -47,5 +49,6 @@ def __init__(self, required_controls=8):
previous_control_position.eq(control_position)
]
self.specials += MultiReg(self.synced, self._r_char_synced.field.w)
+ self.specials += MultiReg(word_sel, self._r_ctl_pos.field.w)
self.sync.pix += self.data.eq(raw >> word_sel)
5 milkymist/dvisampler/decoding.py
View
@@ -13,7 +13,10 @@ def __init__(self):
###
- self.sync.pix += self.output.de.eq(1)
+ self.sync.pix += [
+ self.output.de.eq(1),
+ self.output.c.eq(0)
+ ]
for i, t in enumerate(control_tokens):
self.sync.pix += If(self.input == t,
self.output.de.eq(0),
16 milkymist/dvisampler/edid.py
View
@@ -7,14 +7,14 @@
from migen.bank.description import AutoReg
_default_edid = [
- 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x3D, 0x17, 0x20, 0x11, 0x3E, 0x11, 0x00, 0x00,
- 0x01, 0x17, 0x01, 0x03, 0x80, 0x30, 0x1B, 0x78, 0x08, 0x1D, 0xC5, 0xA4, 0x55, 0x54, 0xA0, 0x27,
- 0x0C, 0x50, 0x54, 0x3F, 0xC0, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
- 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x88, 0x13, 0x20, 0x3C, 0x30, 0x58, 0x2D, 0x20, 0x58, 0x2C,
- 0x45, 0x00, 0xE0, 0x0E, 0x11, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x4D, 0x31, 0x20,
- 0x44, 0x56, 0x49, 0x20, 0x6D, 0x69, 0x78, 0x65, 0x72, 0x0A, 0x00, 0x00, 0x00, 0x10, 0x00, 0x32,
- 0x4C, 0x1E, 0x53, 0x11, 0x00, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0x10,
- 0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x00, 0x2C,
+ 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x3D, 0x17, 0x32, 0x12, 0x2A, 0x6A, 0xBF, 0x00,
+ 0x05, 0x17, 0x01, 0x03, 0x80, 0x28, 0x1E, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x2E, 0x00, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
+ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0xE2, 0x0E, 0x20, 0x20, 0x31, 0x58, 0x13, 0x20, 0x20, 0x80,
+ 0x14, 0x00, 0x28, 0x1E, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x4D, 0x31, 0x20,
+ 0x44, 0x56, 0x49, 0x20, 0x6D, 0x69, 0x78, 0x65, 0x72, 0x0A, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF,
]
class EDID(Module, AutoReg):
71 milkymist/dvisampler/resdetection.py
View
@@ -0,0 +1,71 @@
+from migen.fhdl.structure import *
+from migen.fhdl.module import Module
+from migen.genlib.cdc import MultiReg
+from migen.bank.description import *
+
+class ResolutionDetection(Module, AutoReg):
+ def __init__(self, nbits=10):
+ self.hsync = Signal()
+ self.vsync = Signal()
+ self.de = Signal()
+
+ self._hres = RegisterField(nbits, READ_ONLY, WRITE_ONLY)
+ self._vres = RegisterField(nbits, READ_ONLY, WRITE_ONLY)
+ self._de_cycles = RegisterField(2*nbits, READ_ONLY, WRITE_ONLY)
+
+ ###
+
+ # HRES/VRES
+ hsync_r = Signal()
+ vsync_r = Signal()
+ p_hsync = Signal()
+ p_vsync = Signal()
+ self.sync.pix += [
+ hsync_r.eq(self.hsync),
+ vsync_r.eq(self.vsync),
+ ]
+ self.comb += [
+ p_hsync.eq(self.hsync & ~hsync_r),
+ p_vsync.eq(self.vsync & ~vsync_r)
+ ]
+
+ hcounter = Signal(nbits)
+ vcounter = Signal(nbits)
+ self.sync.pix += [
+ If(p_hsync,
+ hcounter.eq(0)
+ ).Elif(self.de,
+ hcounter.eq(hcounter + 1)
+ ),
+ If(p_vsync,
+ vcounter.eq(0)
+ ).Elif(p_hsync,
+ vcounter.eq(vcounter + 1)
+ )
+ ]
+
+ hcounter_st = Signal(nbits)
+ vcounter_st = Signal(nbits)
+ self.sync.pix += [
+ If(p_hsync & (hcounter != 0), hcounter_st.eq(hcounter)),
+ If(p_vsync & (vcounter != 0), vcounter_st.eq(vcounter))
+ ]
+ self.specials += MultiReg(hcounter_st, self._hres.field.w)
+ self.specials += MultiReg(vcounter_st, self._vres.field.w)
+
+ # DE
+ de_r = Signal()
+ pn_de = Signal()
+ self.sync.pix += de_r.eq(self.de)
+ self.comb += pn_de.eq(~self.de & de_r)
+
+ decounter = Signal(2*nbits)
+ self.sync.pix += If(self.de,
+ decounter.eq(decounter + 1)
+ ).Else(
+ decounter.eq(0)
+ )
+
+ decounter_st = Signal(2*nbits)
+ self.sync.pix += If(pn_de, decounter_st.eq(decounter))
+ self.specials += MultiReg(decounter_st, self._de_cycles.field.w)
4 software/include/base/stddef.h
View
@@ -1,7 +1,11 @@
#ifndef __STDDEF_H
#define __STDDEF_H
+#ifdef __cplusplus
+#define NULL 0
+#else
#define NULL ((void *)0)
+#endif
typedef unsigned long size_t;
typedef long ptrdiff_t;
39 software/include/hw/dvisampler.h
View
@@ -14,20 +14,31 @@
#define CSR_DVISAMPLER0_D0_PHASE DVISAMPLER0_CSR(0x10)
#define CSR_DVISAMPLER0_D0_PHASE_RESET DVISAMPLER0_CSR(0x14)
#define CSR_DVISAMPLER0_D0_CHAR_SYNCED DVISAMPLER0_CSR(0x18)
-
-#define CSR_DVISAMPLER0_D1_DELAY_CTL DVISAMPLER0_CSR(0x1C)
-#define CSR_DVISAMPLER0_D1_DELAY_BUSY DVISAMPLER0_CSR(0x20)
-#define CSR_DVISAMPLER0_D1_PHASE DVISAMPLER0_CSR(0x24)
-#define CSR_DVISAMPLER0_D1_PHASE_RESET DVISAMPLER0_CSR(0x28)
-#define CSR_DVISAMPLER0_D1_CHAR_SYNCED DVISAMPLER0_CSR(0x2C)
-
-#define CSR_DVISAMPLER0_D2_DELAY_CTL DVISAMPLER0_CSR(0x30)
-#define CSR_DVISAMPLER0_D2_DELAY_BUSY DVISAMPLER0_CSR(0x34)
-#define CSR_DVISAMPLER0_D2_PHASE DVISAMPLER0_CSR(0x38)
-#define CSR_DVISAMPLER0_D2_PHASE_RESET DVISAMPLER0_CSR(0x3C)
-#define CSR_DVISAMPLER0_D2_CHAR_SYNCED DVISAMPLER0_CSR(0x40)
-
-#define CSR_DVISAMPLER0_CHAN_SYNCED DVISAMPLER0_CSR(0x44)
+#define CSR_DVISAMPLER0_D0_CTL_POS DVISAMPLER0_CSR(0x1C)
+
+#define CSR_DVISAMPLER0_D1_DELAY_CTL DVISAMPLER0_CSR(0x20)
+#define CSR_DVISAMPLER0_D1_DELAY_BUSY DVISAMPLER0_CSR(0x24)
+#define CSR_DVISAMPLER0_D1_PHASE DVISAMPLER0_CSR(0x28)
+#define CSR_DVISAMPLER0_D1_PHASE_RESET DVISAMPLER0_CSR(0x2C)
+#define CSR_DVISAMPLER0_D1_CHAR_SYNCED DVISAMPLER0_CSR(0x30)
+#define CSR_DVISAMPLER0_D1_CTL_POS DVISAMPLER0_CSR(0x34)
+
+#define CSR_DVISAMPLER0_D2_DELAY_CTL DVISAMPLER0_CSR(0x38)
+#define CSR_DVISAMPLER0_D2_DELAY_BUSY DVISAMPLER0_CSR(0x3C)
+#define CSR_DVISAMPLER0_D2_PHASE DVISAMPLER0_CSR(0x40)
+#define CSR_DVISAMPLER0_D2_PHASE_RESET DVISAMPLER0_CSR(0x44)
+#define CSR_DVISAMPLER0_D2_CHAR_SYNCED DVISAMPLER0_CSR(0x48)
+#define CSR_DVISAMPLER0_D2_CTL_POS DVISAMPLER0_CSR(0x4C)
+
+#define CSR_DVISAMPLER0_CHAN_SYNCED DVISAMPLER0_CSR(0x50)
+
+#define CSR_DVISAMPLER0_HRESH DVISAMPLER0_CSR(0x54)
+#define CSR_DVISAMPLER0_HRESL DVISAMPLER0_CSR(0x58)
+#define CSR_DVISAMPLER0_VRESH DVISAMPLER0_CSR(0x5C)
+#define CSR_DVISAMPLER0_VRESL DVISAMPLER0_CSR(0x60)
+#define CSR_DVISAMPLER0_DECNT2 DVISAMPLER0_CSR(0x64)
+#define CSR_DVISAMPLER0_DECNT1 DVISAMPLER0_CSR(0x68)
+#define CSR_DVISAMPLER0_DECNT0 DVISAMPLER0_CSR(0x6C)
#define DVISAMPLER_DELAY_CAL 0x01
#define DVISAMPLER_DELAY_RST 0x02
50 software/videomixer/main.c
View
@@ -1,4 +1,5 @@
#include <stdio.h>
+#include <stdlib.h>
#include <irq.h>
#include <uart.h>
@@ -6,6 +7,21 @@
static int d0, d1, d2;
+static void print_status(void)
+{
+ printf("Ph: %4d %4d %4d // %d%d%d [%d %d %d] // %d // %dx%d // %d\n", d0, d1, d2,
+ CSR_DVISAMPLER0_D0_CHAR_SYNCED,
+ CSR_DVISAMPLER0_D1_CHAR_SYNCED,
+ CSR_DVISAMPLER0_D2_CHAR_SYNCED,
+ CSR_DVISAMPLER0_D0_CTL_POS,
+ CSR_DVISAMPLER0_D1_CTL_POS,
+ CSR_DVISAMPLER0_D2_CTL_POS,
+ CSR_DVISAMPLER0_CHAN_SYNCED,
+ (CSR_DVISAMPLER0_HRESH << 8) | CSR_DVISAMPLER0_HRESL,
+ (CSR_DVISAMPLER0_VRESH << 8) | CSR_DVISAMPLER0_VRESL,
+ (CSR_DVISAMPLER0_DECNT2 << 16) | (CSR_DVISAMPLER0_DECNT1 << 8) | CSR_DVISAMPLER0_DECNT0);
+}
+
static void calibrate_delays(void)
{
CSR_DVISAMPLER0_D0_DELAY_CTL = DVISAMPLER_DELAY_CAL;
@@ -60,28 +76,46 @@ static void adjust_phase(void)
CSR_DVISAMPLER0_D2_PHASE_RESET = 1;
break;
}
- printf("Ph: %4d %4d %4d // %d%d%d // %d\n", d0, d1, d2,
- CSR_DVISAMPLER0_D0_CHAR_SYNCED,
- CSR_DVISAMPLER0_D1_CHAR_SYNCED,
- CSR_DVISAMPLER0_D2_CHAR_SYNCED,
- CSR_DVISAMPLER0_CHAN_SYNCED);
+}
+
+static int init_phase(void)
+{
+ int od0, od1, od2;
+ int i, j;
+
+ for(i=0;i<100;i++) {
+ od0 = d0;
+ od1 = d1;
+ od2 = d2;
+ for(j=0;j<1000;j++)
+ adjust_phase();
+ if((abs(d0 - od0) < 4) && (abs(d1 - od1) < 4) && (abs(d2 - od2) < 4))
+ return 1;
+ }
+ return 0;
}
static void vmix(void)
{
+ int i;
unsigned int counter;
while(1) {
while(!CSR_DVISAMPLER0_PLL_LOCKED);
printf("PLL locked\n");
calibrate_delays();
- adjust_phase();
+ if(init_phase())
+ printf("Phase init OK\n");
+ else
+ printf("Phase did not settle\n");
+ print_status();
counter = 0;
while(CSR_DVISAMPLER0_PLL_LOCKED) {
counter++;
- if(counter == 200000) {
- adjust_phase();
+ if(counter == 2000000) {
+ print_status();
+ //adjust_phase();
counter = 0;
}
}

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