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  1. 1  .gitignore
  2. 8  build.py
  3. 63  cif.py
  4. 10  cmacros.py
  5. 16  common/csrbase.h
  6. 8  common/interrupt.h
  7. 3  software/bios/isr.c
  8. 13  software/bios/main.c
  9. 45  software/bios/microudp.c
  10. 2  software/bios/microudp.h
  11. 64  software/bios/sdram.c
  12. 8  software/include/base/board.h
  13. 8  software/include/base/console.h
  14. 8  software/include/base/crc.h
  15. 8  software/include/base/ctype.h
  16. 8  software/include/base/endian.h
  17. 8  software/include/base/errno.h
  18. 8  software/include/base/float.h
  19. 8  software/include/base/irq.h
  20. 8  software/include/base/limits.h
  21. 9  software/include/base/setjmp.h
  22. 8  software/include/base/stdarg.h
  23. 8  software/include/base/stddef.h
  24. 8  software/include/base/stdint.h
  25. 7  software/include/base/stdio.h
  26. 8  software/include/base/stdlib.h
  27. 8  software/include/base/string.h
  28. 10  software/include/base/system.h
  29. 8  software/include/base/timer.h
  30. 8  software/include/base/uart.h
  31. 65  software/include/hw/dfii.h
  32. 51  software/include/hw/dvisampler.h
  33. 21  software/include/hw/flags.h
  34. 18  software/include/hw/gpio.h
  35. 18  software/include/hw/identifier.h
  36. 4  software/include/hw/mem.h
  37. 32  software/include/hw/minimac.h
  38. 27  software/include/hw/timer.h
  39. 20  software/include/hw/uart.h
  40. 16  software/libbase/board.c
  41. 25  software/libbase/timer.c
  42. 22  software/libbase/uart.c
  43. 49  top.py
1  .gitignore
@@ -9,3 +9,4 @@ tools/bin2hex
9 9
 tools/flterm
10 10
 tools/mkmmimg
11 11
 tools/byteswap
  12
+software/include/hw/csr.h
8  build.py
... ...
@@ -1,8 +1,12 @@
1 1
 #!/usr/bin/env python3
2 2
 
3 3
 import os
  4
+
4 5
 from mibuild.platforms import m1
  6
+from mibuild.tools import write_to_file
  7
+
5 8
 import top
  9
+import cif
6 10
 
7 11
 def main():
8 12
 	plat = m1.Platform()
@@ -68,8 +72,10 @@ def main():
68 72
 		"lm32_dcache.v", "lm32_top.v", "lm32_debug.v", "lm32_jtag.v", "jtag_cores.v",
69 73
 		"jtag_tap_spartan6.v", "lm32_itlb.v", "lm32_dtlb.v")
70 74
 	plat.add_sources(os.path.join("verilog", "lm32"), "lm32_config.v")
71  
-	
  75
+
72 76
 	plat.build_cmdline(soc)
  77
+	csr_header = cif.get_csr_header(soc.csr_base, soc.csrbankarray, soc.interrupt_map)
  78
+	write_to_file("software/include/hw/csr.h", csr_header)
73 79
 
74 80
 if __name__ == "__main__":
75 81
 	main()
63  cif.py
... ...
@@ -0,0 +1,63 @@
  1
+from operator import itemgetter
  2
+import re
  3
+
  4
+def get_macros(filename):
  5
+	f = open(filename, "r")
  6
+	r = {}
  7
+	for line in f:
  8
+		match = re.match("\w*#define\s+(\w+)\s+(.*)", line, re.IGNORECASE)
  9
+		if match:
  10
+			r[match.group(1)] = match.group(2)
  11
+	return r
  12
+
  13
+def _get_rw_functions(reg_name, reg_base, size):
  14
+	r = ""
  15
+	if size > 8:
  16
+		raise NotImplementedError("Register too large")
  17
+	elif size > 4:
  18
+		ctype = "unsigned long long int"
  19
+	elif size > 2:
  20
+		ctype = "unsigned int"
  21
+	elif size > 1:
  22
+		ctype = "unsigned short int"
  23
+	else:
  24
+		ctype = "unsigned char"
  25
+
  26
+	r += "static inline "+ctype+" "+reg_name+"_read(void) {\n"
  27
+	if size > 1:
  28
+		r += "\t"+ctype+" r = MMPTR("+hex(reg_base)+");\n"
  29
+		for byte in range(1, size):
  30
+			r += "\tr <<= 8;\n\tr |= MMPTR("+hex(reg_base+4*byte)+");\n"
  31
+		r += "\treturn r;\n}\n"
  32
+	else:
  33
+		r += "\treturn MMPTR("+hex(reg_base)+");\n}\n"
  34
+
  35
+	r += "static inline void "+reg_name+"_write("+ctype+" value) {\n"
  36
+	for byte in range(size):
  37
+		shift = (size-byte-1)*8
  38
+		if shift:
  39
+			value_shifted = "value >> "+str(shift)
  40
+		else:
  41
+			value_shifted = "value"
  42
+		r += "\tMMPTR("+hex(reg_base+4*byte)+") = "+value_shifted+";\n"
  43
+	r += "}\n"
  44
+	return r
  45
+
  46
+def get_csr_header(csr_base, bank_array, interrupt_map):
  47
+	r = "#ifndef __HW_CSR_H\n#define __HW_CSR_H\n#include <hw/common.h>\n"
  48
+	for name, rmap in bank_array.banks:
  49
+		r += "\n/* "+name+" */\n"
  50
+		reg_base = csr_base + 0x800*rmap.address
  51
+		r += "#define "+name.upper()+"_BASE "+hex(reg_base)+"\n"
  52
+		for register in rmap.description:
  53
+			nr = (register.get_size() + 7)//8
  54
+			r += _get_rw_functions(name + "_" + register.name, reg_base, nr)
  55
+			reg_base += 4*nr
  56
+		try:
  57
+			interrupt_nr = interrupt_map[name]
  58
+		except KeyError:
  59
+			pass
  60
+		else:
  61
+			r += "#define "+name.upper()+"_INTERRUPT "+str(interrupt_nr)+"\n"
  62
+	r += "\n#endif\n"
  63
+	return r
10  cmacros.py
... ...
@@ -1,10 +0,0 @@
1  
-import re
2  
-
3  
-def get_macros(filename):
4  
-	f = open(filename, "r")
5  
-	r = {}
6  
-	for line in f:
7  
-		match = re.match("\w*#define\s+(\w+)\s+(.*)", line, re.IGNORECASE)
8  
-		if match:
9  
-			r[match.group(1)] = match.group(2)
10  
-	return r
16  common/csrbase.h
... ...
@@ -1,16 +0,0 @@
1  
-#ifndef __CSRBASE_H
2  
-#define __CSRBASE_H
3  
-
4  
-#define UART_BASE			0xe0000000
5  
-#define DFII_BASE			0xe0000800
6  
-#define IDENTIFIER_BASE			0xe0001000
7  
-#define TIMER0_BASE			0xe0001800
8  
-#define MINIMAC_BASE			0xe0002000
9  
-#define FB_BASE				0xe0002800
10  
-#define ASMIPROBE_BASE			0xe0003000
11  
-#define DVISAMPLER0_BASE		0xe0003800
12  
-#define DVISAMPLER0_EDID_MEM_BASE	0xe0004000
13  
-#define DVISAMPLER1_BASE		0xe0004800
14  
-#define DVISAMPLER1_EDID_MEM_BASE	0xe0005000
15  
-
16  
-#endif /* __CSRBASE_H */
8  common/interrupt.h
... ...
@@ -1,8 +0,0 @@
1  
-#ifndef __INTERRUPT_H
2  
-#define __INTERRUPT_H
3  
-
4  
-#define UART_INTERRUPT		0
5  
-#define TIMER0_INTERRUPT	1
6  
-#define MINIMAC_INTERRUPT	2
7  
-
8  
-#endif /* __INTERRUPT_H */
3  software/bios/isr.c
... ...
@@ -1,5 +1,4 @@
1  
-#include <hw/uart.h>
2  
-#include <interrupt.h>
  1
+#include <hw/csr.h>
3 2
 #include <irq.h>
4 3
 #include <uart.h>
5 4
 
13  software/bios/main.c
@@ -11,11 +11,11 @@
11 11
 #include <timer.h>
12 12
 
13 13
 #include <hw/mem.h>
14  
-#include <hw/minimac.h>
15 14
 
16 15
 #include "sdram.h"
17 16
 #include "dataflow.h"
18 17
 #include "boot.h"
  18
+#include "microudp.h"
19 19
 
20 20
 enum {
21 21
 	CSR_IE = 1, CSR_IM, CSR_IP, CSR_ICC, CSR_DCC, CSR_CC, CSR_CFG, CSR_EBA,
@@ -403,17 +403,6 @@ static void crcbios(void)
403 403
 	}
404 404
 }
405 405
 
406  
-static void ethreset(void)
407  
-{
408  
-	CSR_MINIMAC_PHYRST = 0;
409  
-	busy_wait(2);
410  
-	/* that pesky ethernet PHY needs two resets at times... */
411  
-	CSR_MINIMAC_PHYRST = 1;
412  
-	busy_wait(2);
413  
-	CSR_MINIMAC_PHYRST = 0;
414  
-	busy_wait(2);
415  
-}
416  
-
417 406
 static void print_mac(void)
418 407
 {
419 408
 	unsigned char *macadr = (unsigned char *)FLASH_OFFSET_MAC_ADDRESS;
45  software/bios/microudp.c
... ...
@@ -1,7 +1,10 @@
1 1
 #include <stdio.h>
2 2
 #include <system.h>
3 3
 #include <crc.h>
4  
-#include <hw/minimac.h>
  4
+#include <timer.h>
  5
+#include <hw/csr.h>
  6
+#include <hw/flags.h>
  7
+#include <hw/mem.h>
5 8
 
6 9
 #include "microudp.h"
7 10
 
@@ -93,11 +96,11 @@ typedef union {
93 96
 } ethernet_buffer;
94 97
 
95 98
 
96  
-static int rxlen;
  99
+static unsigned int rxlen;
97 100
 static ethernet_buffer *rxbuffer;
98 101
 static ethernet_buffer *rxbuffer0;
99 102
 static ethernet_buffer *rxbuffer1;
100  
-static int txlen;
  103
+static unsigned int txlen;
101 104
 static ethernet_buffer *txbuffer;
102 105
 
103 106
 static void send_packet(void)
@@ -110,11 +113,10 @@ static void send_packet(void)
110 113
 	txbuffer->raw[txlen+2] = (crc & 0xff0000) >> 16;
111 114
 	txbuffer->raw[txlen+3] = (crc & 0xff000000) >> 24;
112 115
 	txlen += 4;
113  
-	CSR_MINIMAC_TXCOUNTH = (txlen & 0xff00) >> 8;
114  
-	CSR_MINIMAC_TXCOUNTL = txlen & 0x00ff;
115  
-	CSR_MINIMAC_TXSTART = 1;
116  
-	while(!(CSR_MINIMAC_EV_PENDING & MINIMAC_EV_TX));
117  
-	CSR_MINIMAC_EV_PENDING = MINIMAC_EV_TX;
  116
+	minimac_tx_count_write(txlen);
  117
+	minimac_tx_start_write(1);
  118
+	while(!(minimac_ev_pending_read() & MINIMAC_EV_TX));
  119
+	minimac_ev_pending_write(MINIMAC_EV_TX);
118 120
 }
119 121
 
120 122
 static unsigned char my_mac[6];
@@ -215,7 +217,7 @@ int microudp_arp_resolve(unsigned int ip)
215 217
 static unsigned short ip_checksum(unsigned int r, void *buffer, unsigned int length, int complete)
216 218
 {
217 219
 	unsigned char *ptr;
218  
-	int i;
  220
+	unsigned int i;
219 221
 
220 222
 	ptr = (unsigned char *)buffer;
221 223
 	length >>= 1;
@@ -349,7 +351,7 @@ void microudp_start(unsigned char *macaddr, unsigned int ip)
349 351
 {
350 352
 	int i;
351 353
 
352  
-	CSR_MINIMAC_EV_PENDING = MINIMAC_EV_RX0 | MINIMAC_EV_RX1 | MINIMAC_EV_TX;
  354
+	minimac_ev_pending_write(MINIMAC_EV_RX0 | MINIMAC_EV_RX1 | MINIMAC_EV_TX);
353 355
 	
354 356
 	rxbuffer0 = (ethernet_buffer *)MINIMAC_RX0_BASE;
355 357
 	rxbuffer1 = (ethernet_buffer *)MINIMAC_RX1_BASE;
@@ -368,16 +370,27 @@ void microudp_start(unsigned char *macaddr, unsigned int ip)
368 370
 
369 371
 void microudp_service(void)
370 372
 {
371  
-	if(CSR_MINIMAC_EV_PENDING & MINIMAC_EV_RX0) {
372  
-		rxlen = (CSR_MINIMAC_RXCOUNT0H << 8) | CSR_MINIMAC_RXCOUNT0L;
  373
+	if(minimac_ev_pending_read() & MINIMAC_EV_RX0) {
  374
+		rxlen = minimac_rx_count_0_read();
373 375
 		rxbuffer = rxbuffer0;
374 376
 		process_frame();
375  
-		CSR_MINIMAC_EV_PENDING = MINIMAC_EV_RX0;
  377
+		minimac_ev_pending_write(MINIMAC_EV_RX0);
376 378
 	}
377  
-	if(CSR_MINIMAC_EV_PENDING & MINIMAC_EV_RX1) {
378  
-		rxlen = (CSR_MINIMAC_RXCOUNT1H << 8) | CSR_MINIMAC_RXCOUNT1L;
  379
+	if(minimac_ev_pending_read() & MINIMAC_EV_RX1) {
  380
+		rxlen = minimac_rx_count_1_read();
379 381
 		rxbuffer = rxbuffer1;
380 382
 		process_frame();
381  
-		CSR_MINIMAC_EV_PENDING = MINIMAC_EV_RX1;
  383
+		minimac_ev_pending_write(MINIMAC_EV_RX1);
382 384
 	}
383 385
 }
  386
+
  387
+void ethreset(void)
  388
+{
  389
+	minimac_phy_reset_write(0);
  390
+	busy_wait(2);
  391
+	/* that pesky ethernet PHY needs two resets at times... */
  392
+	minimac_phy_reset_write(1);
  393
+	busy_wait(2);
  394
+	minimac_phy_reset_write(0);
  395
+	busy_wait(2);
  396
+}
2  software/bios/microudp.h
@@ -14,4 +14,6 @@ int microudp_send(unsigned short src_port, unsigned short dst_port, unsigned int
14 14
 void microudp_set_callback(udp_callback callback);
15 15
 void microudp_service(void);
16 16
 
  17
+void ethreset(void);
  18
+
17 19
 #endif /* __MICROUDP_H */
64  software/bios/sdram.c
... ...
@@ -1,9 +1,9 @@
1 1
 #include <stdio.h>
2 2
 #include <stdlib.h>
3 3
 
4  
-#include <hw/dfii.h>
  4
+#include <hw/csr.h>
  5
+#include <hw/flags.h>
5 6
 #include <hw/mem.h>
6  
-#include <csrbase.h>
7 7
 
8 8
 #include "sdram.h"
9 9
 
@@ -15,24 +15,16 @@ static void cdelay(int i)
15 15
 	}
16 16
 }
17 17
 
18  
-static void setaddr(int a)
19  
-{
20  
-	CSR_DFII_AH_P0 = (a & 0xff00) >> 8;
21  
-	CSR_DFII_AL_P0 = a & 0x00ff;
22  
-	CSR_DFII_AH_P1 = (a & 0xff00) >> 8;
23  
-	CSR_DFII_AL_P1 = a & 0x00ff;
24  
-}
25  
-
26 18
 static void command_p0(int cmd)
27 19
 {
28  
-	CSR_DFII_COMMAND_P0 = cmd;
29  
-	CSR_DFII_COMMAND_ISSUE_P0 = 1;
  20
+	dfii_pi0_command_write(cmd);
  21
+	dfii_pi0_command_issue_write(1);
30 22
 }
31 23
 
32 24
 static void command_p1(int cmd)
33 25
 {
34  
-	CSR_DFII_COMMAND_P1 = cmd;
35  
-	CSR_DFII_COMMAND_ISSUE_P1 = 1;
  26
+	dfii_pi1_command_write(cmd);
  27
+	dfii_pi1_command_issue_write(1);
36 28
 }
37 29
 
38 30
 static void init_sequence(void)
@@ -40,51 +32,51 @@ static void init_sequence(void)
40 32
 	int i;
41 33
 	
42 34
 	/* Bring CKE high */
43  
-	setaddr(0x0000);
44  
-	CSR_DFII_BA_P0 = 0;
45  
-	CSR_DFII_CONTROL = DFII_CONTROL_CKE;
  35
+	dfii_pi0_address_write(0x0000);
  36
+	dfii_pi0_baddress_write(0);
  37
+	dfii_control_write(DFII_CONTROL_CKE);
46 38
 	
47 39
 	/* Precharge All */
48  
-	setaddr(0x0400);
  40
+	dfii_pi0_address_write(0x0400);
49 41
 	command_p0(DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
50 42
 	
51 43
 	/* Load Extended Mode Register */
52  
-	CSR_DFII_BA_P0 = 1;
53  
-	setaddr(0x0000);
  44
+	dfii_pi0_baddress_write(1);
  45
+	dfii_pi0_address_write(0x0000);
54 46
 	command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
55  
-	CSR_DFII_BA_P0 = 0;
  47
+	dfii_pi0_baddress_write(0);
56 48
 	
57 49
 	/* Load Mode Register */
58  
-	setaddr(0x0132); /* Reset DLL, CL=3, BL=4 */
  50
+	dfii_pi0_address_write(0x0132); /* Reset DLL, CL=3, BL=4 */
59 51
 	command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
60 52
 	cdelay(200);
61 53
 	
62 54
 	/* Precharge All */
63  
-	setaddr(0x0400);
  55
+	dfii_pi0_address_write(0x0400);
64 56
 	command_p0(DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
65 57
 	
66 58
 	/* 2x Auto Refresh */
67 59
 	for(i=0;i<2;i++) {
68  
-		setaddr(0);
  60
+		dfii_pi0_address_write(0);
69 61
 		command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_CS);
70 62
 		cdelay(4);
71 63
 	}
72 64
 	
73 65
 	/* Load Mode Register */
74  
-	setaddr(0x0032); /* CL=3, BL=4 */
  66
+	dfii_pi0_address_write(0x0032); /* CL=3, BL=4 */
75 67
 	command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
76 68
 	cdelay(200);
77 69
 }
78 70
 
79 71
 void ddrsw(void)
80 72
 {
81  
-	CSR_DFII_CONTROL = DFII_CONTROL_CKE;
  73
+	dfii_control_write(DFII_CONTROL_CKE);
82 74
 	printf("DDR now under software control\n");
83 75
 }
84 76
 
85 77
 void ddrhw(void)
86 78
 {
87  
-	CSR_DFII_CONTROL = DFII_CONTROL_SEL|DFII_CONTROL_CKE;
  79
+	dfii_control_write(DFII_CONTROL_SEL|DFII_CONTROL_CKE);
88 80
 	printf("DDR now under hardware control\n");
89 81
 }
90 82
 
@@ -94,8 +86,8 @@ void ddrrow(char *_row)
94 86
 	unsigned int row;
95 87
 	
96 88
 	if(*_row == 0) {
97  
-		setaddr(0x0000);
98  
-		CSR_DFII_BA_P0 = 0;
  89
+		dfii_pi0_address_write(0x0000);
  90
+		dfii_pi0_baddress_write(0);
99 91
 		command_p0(DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
100 92
 		cdelay(15);
101 93
 		printf("Precharged\n");
@@ -105,8 +97,8 @@ void ddrrow(char *_row)
105 97
 			printf("incorrect row\n");
106 98
 			return;
107 99
 		}
108  
-		setaddr(row);
109  
-		CSR_DFII_BA_P0 = 0;
  100
+		dfii_pi0_address_write(row);
  101
+		dfii_pi0_baddress_write(0);
110 102
 		command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CS);
111 103
 		cdelay(15);
112 104
 		printf("Activated row %d\n", row);
@@ -129,8 +121,8 @@ void ddrrd(char *startaddr)
129 121
 		return;
130 122
 	}
131 123
 	
132  
-	setaddr(addr);
133  
-	CSR_DFII_BA_P0 = 0;
  124
+	dfii_pi0_address_write(addr);
  125
+	dfii_pi0_baddress_write(0);
134 126
 	command_p0(DFII_COMMAND_CAS|DFII_COMMAND_CS|DFII_COMMAND_RDDATA);
135 127
 	cdelay(15);
136 128
 	
@@ -162,8 +154,8 @@ void ddrwr(char *startaddr)
162 154
 		MMPTR(0xe0000864+4*i) = 0xf0 + i;
163 155
 	}
164 156
 	
165  
-	setaddr(addr);
166  
-	CSR_DFII_BA_P1 = 0;
  157
+	dfii_pi1_address_write(addr);
  158
+	dfii_pi1_baddress_write(0);
167 159
 	command_p1(DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS|DFII_COMMAND_WRDATA);
168 160
 }
169 161
 
@@ -211,7 +203,7 @@ int ddrinit(void)
211 203
 	printf("Initializing DDR SDRAM...\n");
212 204
 	
213 205
 	init_sequence();
214  
-	CSR_DFII_CONTROL = DFII_CONTROL_SEL|DFII_CONTROL_CKE;
  206
+	dfii_control_write(DFII_CONTROL_SEL|DFII_CONTROL_CKE);
215 207
 	if(!memtest())
216 208
 		return 0;
217 209
 	
8  software/include/base/board.h
... ...
@@ -1,6 +1,10 @@
1 1
 #ifndef __BOARD_H
2 2
 #define __BOARD_H
3 3
 
  4
+#ifdef __cplusplus
  5
+extern "C" {
  6
+#endif
  7
+
4 8
 #define BOARD_NAME_LEN 32
5 9
 
6 10
 struct board_desc {
@@ -16,4 +20,8 @@ void get_soc_version_formatted(char *version);
16 20
 extern const struct board_desc *brd_desc;
17 21
 void board_init(void);
18 22
 
  23
+#ifdef __cplusplus
  24
+}
  25
+#endif
  26
+
19 27
 #endif /* __BOARD_H */
8  software/include/base/console.h
... ...
@@ -1,6 +1,10 @@
1 1
 #ifndef __CONSOLE_H
2 2
 #define __CONSOLE_H
3 3
 
  4
+#ifdef __cplusplus
  5
+extern "C" {
  6
+#endif
  7
+
4 8
 typedef void (*console_write_hook)(char);
5 9
 typedef char (*console_read_hook)(void);
6 10
 typedef int (*console_read_nonblock_hook)(void);
@@ -13,4 +17,8 @@ int readchar_nonblock(void);
13 17
 
14 18
 void putsnonl(const char *s);
15 19
 
  20
+#ifdef __cplusplus
  21
+}
  22
+#endif
  23
+
16 24
 #endif /* __CONSOLE_H */
8  software/include/base/crc.h
... ...
@@ -1,7 +1,15 @@
1 1
 #ifndef __CRC_H
2 2
 #define __CRC_H
3 3
 
  4
+#ifdef __cplusplus
  5
+extern "C" {
  6
+#endif
  7
+
4 8
 unsigned short crc16(const unsigned char *buffer, int len);
5 9
 unsigned int crc32(const unsigned char *buffer, unsigned int len);
6 10
 
  11
+#ifdef __cplusplus
  12
+}
  13
+#endif
  14
+
7 15
 #endif
8  software/include/base/ctype.h
... ...
@@ -1,6 +1,10 @@
1 1
 #ifndef __CTYPE_H
2 2
 #define __CTYPE_H
3 3
 
  4
+#ifdef __cplusplus
  5
+extern "C" {
  6
+#endif
  7
+
4 8
 /*
5 9
  * NOTE! This ctype does not handle EOF like the standard C
6 10
  * library is required to.
@@ -52,4 +56,8 @@ static inline unsigned char __toupper(unsigned char c)
52 56
 #define tolower(c) __tolower(c)
53 57
 #define toupper(c) __toupper(c)
54 58
 
  59
+#ifdef __cplusplus
  60
+}
  61
+#endif
  62
+
55 63
 #endif /* __CTYPE_H */
8  software/include/base/endian.h
... ...
@@ -1,6 +1,10 @@
1 1
 #ifndef __ENDIAN_H
2 2
 #define __ENDIAN_H
3 3
 
  4
+#ifdef __cplusplus
  5
+extern "C" {
  6
+#endif
  7
+
4 8
 #define __LITTLE_ENDIAN 0
5 9
 #define __BIG_ENDIAN 1
6 10
 #define __BYTE_ORDER __BIG_ENDIAN
@@ -19,4 +23,8 @@ static inline unsigned short le16toh(unsigned short val)
19 23
 		(val & 0xff00) >> 8;
20 24
 }
21 25
 
  26
+#ifdef __cplusplus
  27
+}
  28
+#endif
  29
+
22 30
 #endif /* __ENDIAN_H */
8  software/include/base/errno.h
... ...
@@ -1,6 +1,10 @@
1 1
 #ifndef __ERRNO_H
2 2
 #define __ERRNO_H
3 3
 
  4
+#ifdef __cplusplus
  5
+extern "C" {
  6
+#endif
  7
+
4 8
 extern int errno;
5 9
 
6 10
 #define EPERM               1
@@ -250,4 +254,8 @@ extern int errno;
250 254
 #define EMEDIUMTYPE         124
251 255
 #define EMEDIUMTYPE_STR     "Wrong medium type"
252 256
 
  257
+#ifdef __cplusplus
  258
+}
  259
+#endif
  260
+
253 261
 #endif /* __ERRNO_H */
8  software/include/base/float.h
... ...
@@ -1,6 +1,10 @@
1 1
 #ifndef __FLOAT_H
2 2
 #define __FLOAT_H
3 3
 
  4
+#ifdef __cplusplus
  5
+extern "C" {
  6
+#endif
  7
+
4 8
 #define FLT_EVAL_METHOD __FLT_EVAL_METHOD__
5 9
 #define FLT_ROUNDS (__builtin_flt_rounds())
6 10
 #define FLT_RADIX __FLT_RADIX__
@@ -47,4 +51,8 @@
47 51
 #define DBL_TRUE_MIN __DBL_DENORM_MIN__
48 52
 #define LDBL_TRUE_MIN __LDBL_DENORM_MIN__
49 53
 
  54
+#ifdef __cplusplus
  55
+}
  56
+#endif
  57
+
50 58
 #endif /* __FLOAT_H */
8  software/include/base/irq.h
... ...
@@ -1,6 +1,10 @@
1 1
 #ifndef __IRQ_H
2 2
 #define __IRQ_H
3 3
 
  4
+#ifdef __cplusplus
  5
+extern "C" {
  6
+#endif
  7
+
4 8
 static inline unsigned int irq_getie(void)
5 9
 {
6 10
        unsigned int ie;
@@ -32,4 +36,8 @@ static inline unsigned int irq_pending(void)
32 36
        return pending;
33 37
 }
34 38
 
  39
+#ifdef __cplusplus
  40
+}
  41
+#endif
  42
+
35 43
 #endif /* __IRQ_H */
8  software/include/base/limits.h
... ...
@@ -1,6 +1,10 @@
1 1
 #ifndef __LIMITS_H
2 2
 #define __LIMITS_H
3 3
 
  4
+#ifdef __cplusplus
  5
+extern "C" {
  6
+#endif
  7
+
4 8
 #define ULONG_MAX 0xffffffff
5 9
 
6 10
 #define UINT_MAX 0xffffffff
@@ -15,4 +19,8 @@
15 19
 
16 20
 #define CHAR_BIT 8
17 21
 
  22
+#ifdef __cplusplus
  23
+}
  24
+#endif
  25
+
18 26
 #endif /* __LIMITS_H */
9  software/include/base/setjmp.h
... ...
@@ -1,6 +1,10 @@
1 1
 #ifndef __SETJMP_H
2 2
 #define __SETJMP_H
3 3
 
  4
+#ifdef __cplusplus
  5
+extern "C" {
  6
+#endif
  7
+
4 8
 #define _JBLEN 19
5 9
 
6 10
 typedef	int jmp_buf[_JBLEN];
@@ -8,5 +12,8 @@ typedef	int jmp_buf[_JBLEN];
8 12
 int setjmp(jmp_buf env);
9 13
 void longjmp(jmp_buf env, int val);
10 14
 
11  
-#endif /* __SETJMP_H */
  15
+#ifdef __cplusplus
  16
+}
  17
+#endif
12 18
 
  19
+#endif /* __SETJMP_H */
8  software/include/base/stdarg.h
@@ -3,6 +3,10 @@
3 3
 
4 4
 #include <stdlib.h>
5 5
 
  6
+#ifdef __cplusplus
  7
+extern "C" {
  8
+#endif
  9
+
6 10
 #define va_start(v, l) __builtin_va_start((v), l)
7 11
 #define va_arg(ap, type) __builtin_va_arg((ap), type)
8 12
 #define va_copy(aq, ap) __builtin_va_copy((aq), (ap))
@@ -13,4 +17,8 @@ int vsnprintf(char *buf, size_t size, const char *fmt, va_list args);
13 17
 int vscnprintf(char *buf, size_t size, const char *fmt, va_list args);
14 18
 int vsprintf(char *buf, const char *fmt, va_list args);
15 19
 
  20
+#ifdef __cplusplus
  21
+}
  22
+#endif
  23
+
16 24
 #endif /* __STDARG_H */
8  software/include/base/stddef.h
@@ -2,6 +2,10 @@
2 2
 #define __STDDEF_H
3 3
 
4 4
 #ifdef __cplusplus
  5
+extern "C" {
  6
+#endif
  7
+
  8
+#ifdef __cplusplus
5 9
 #define NULL 0
6 10
 #else
7 11
 #define NULL ((void *)0)
@@ -12,4 +16,8 @@ typedef long ptrdiff_t;
12 16
 
13 17
 #define offsetof(s,m) (size_t)&(((s *)0)->m)
14 18
 
  19
+#ifdef __cplusplus
  20
+}
  21
+#endif
  22
+
15 23
 #endif /* __STDDEF_H */
8  software/include/base/stdint.h
... ...
@@ -1,6 +1,10 @@
1 1
 #ifndef __STDINT_H
2 2
 #define __STDINT_H
3 3
 
  4
+#ifdef __cplusplus
  5
+extern "C" {
  6
+#endif
  7
+
4 8
 typedef unsigned int uintptr_t;
5 9
 
6 10
 typedef unsigned long long uint64_t;
@@ -22,4 +26,8 @@ typedef char int8_t;
22 26
 #define INT32_C(v) v
23 27
 #define UINT32_C(v) v##U
24 28
 
  29
+#ifdef __cplusplus
  30
+}
  31
+#endif
  32
+
25 33
 #endif /* __STDINT_H */
7  software/include/base/stdio.h
@@ -3,6 +3,10 @@
3 3
 
4 4
 #include <stddef.h>
5 5
 
  6
+#ifdef __cplusplus
  7
+extern "C" {
  8
+#endif
  9
+
6 10
 int putchar(int c);
7 11
 int puts(const char *s);
8 12
 
@@ -66,5 +70,8 @@ int fclose(FILE *fp);
66 70
 int fseek(FILE *stream, long offset, int whence);
67 71
 long ftell(FILE *stream);
68 72
 
  73
+#ifdef __cplusplus
  74
+}
  75
+#endif
69 76
 
70 77
 #endif /* __STDIO_H */
8  software/include/base/stdlib.h
@@ -21,6 +21,10 @@
21 21
 
22 22
 #include <stddef.h>
23 23
 
  24
+#ifdef __cplusplus
  25
+extern "C" {
  26
+#endif
  27
+
24 28
 #define PRINTF_ZEROPAD	1		/* pad with zero */
25 29
 #define PRINTF_SIGN	2		/* unsigned/signed long */
26 30
 #define PRINTF_PLUS	4		/* show plus */
@@ -72,4 +76,8 @@ void *malloc(size_t size);
72 76
 void free(void *ptr);
73 77
 void *realloc(void *ptr, size_t size);
74 78
 
  79
+#ifdef __cplusplus
  80
+}
  81
+#endif
  82
+
75 83
 #endif /* __STDLIB_H */
8  software/include/base/string.h
@@ -21,6 +21,10 @@
21 21
 
22 22
 #include <stddef.h>
23 23
 
  24
+#ifdef __cplusplus
  25
+extern "C" {
  26
+#endif
  27
+
24 28
 char *strchr(const char *s, int c);
25 29
 char *strpbrk(const char *,const char *);
26 30
 char *strrchr(const char *s, int c);
@@ -43,4 +47,8 @@ void *memchr(const void *s, int c, size_t n);
43 47
 
44 48
 char *strerror(int errnum);
45 49
 
  50
+#ifdef __cplusplus
  51
+}
  52
+#endif
  53
+
46 54
 #endif /* __STRING_H */
10  software/include/base/system.h
... ...
@@ -1,9 +1,15 @@
1 1
 #ifndef __SYSTEM_H
2 2
 #define __SYSTEM_H
3 3
 
  4
+#ifdef __cplusplus
  5
+extern "C" {
  6
+#endif
  7
+
4 8
 void flush_cpu_icache(void);
5 9
 void flush_cpu_dcache(void);
6  
-__attribute__((noreturn)) void reboot(void);
7  
-__attribute__((noreturn)) void reconf(void);
  10
+
  11
+#ifdef __cplusplus
  12
+}
  13
+#endif
8 14
 
9 15
 #endif /* __SYSTEM_H */
8  software/include/base/timer.h
... ...
@@ -1,6 +1,10 @@
1 1
 #ifndef __TIMER_H
2 2
 #define __TIMER_H
3 3
 
  4
+#ifdef __cplusplus
  5
+extern "C" {
  6
+#endif
  7
+
4 8
 unsigned int get_system_frequency(void);
5 9
 void timer_enable(int en);
6 10
 unsigned int timer_get(void);
@@ -8,4 +12,8 @@ void timer_set_counter(unsigned int value);
8 12
 void timer_set_reload(unsigned int value);
9 13
 void busy_wait(unsigned int ms);
10 14
 
  15
+#ifdef __cplusplus
  16
+}
  17
+#endif
  18
+
11 19
 #endif /* __TIMER_H */
8  software/include/base/uart.h
... ...
@@ -1,6 +1,10 @@
1 1
 #ifndef __UART_H
2 2
 #define __UART_H
3 3
 
  4
+#ifdef __cplusplus
  5
+extern "C" {
  6
+#endif
  7
+
4 8
 void uart_init(void);
5 9
 void uart_isr(void);
6 10
 void uart_sync(void);
@@ -9,4 +13,8 @@ void uart_write(char c);
9 13
 char uart_read(void);
10 14
 int uart_read_nonblock(void);
11 15
 
  16
+#ifdef __cplusplus
  17
+}
  18
+#endif
  19
+
12 20
 #endif
65  software/include/hw/dfii.h
... ...
@@ -1,65 +0,0 @@
1  
-#ifndef __HW_DFII_H
2  
-#define __HW_DFII_H
3  
-
4  
-#include <hw/common.h>
5  
-#include <csrbase.h>
6  
-
7  
-#define DFII_CSR(x)			MMPTR(DFII_BASE+(x))
8  
-
9  
-#define CSR_DFII_CONTROL		DFII_CSR(0x00)
10  
-
11  
-#define DFII_CONTROL_SEL		0x01
12  
-#define DFII_CONTROL_CKE		0x02
13  
-
14  
-#define CSR_DFII_COMMAND_P0		DFII_CSR(0x04)
15  
-#define CSR_DFII_COMMAND_ISSUE_P0	DFII_CSR(0x08)
16  
-#define CSR_DFII_AH_P0			DFII_CSR(0x0C)
17  
-#define CSR_DFII_AL_P0			DFII_CSR(0x10)
18  
-#define CSR_DFII_BA_P0			DFII_CSR(0x14)
19  
-#define CSR_DFII_WD0_P0			DFII_CSR(0x18)
20  
-#define CSR_DFII_WD1_P0			DFII_CSR(0x1C)
21  
-#define CSR_DFII_WD2_P0			DFII_CSR(0x20)
22  
-#define CSR_DFII_WD3_P0			DFII_CSR(0x24)
23  
-#define CSR_DFII_WD4_P0			DFII_CSR(0x28)
24  
-#define CSR_DFII_WD5_P0			DFII_CSR(0x2C)
25  
-#define CSR_DFII_WD6_P0			DFII_CSR(0x30)
26  
-#define CSR_DFII_WD7_P0			DFII_CSR(0x34)
27  
-#define CSR_DFII_RD0_P0			DFII_CSR(0x38)
28  
-#define CSR_DFII_RD1_P0			DFII_CSR(0x3C)
29  
-#define CSR_DFII_RD2_P0			DFII_CSR(0x40)
30  
-#define CSR_DFII_RD3_P0			DFII_CSR(0x44)
31  
-#define CSR_DFII_RD4_P0			DFII_CSR(0x48)
32  
-#define CSR_DFII_RD5_P0			DFII_CSR(0x4C)
33  
-#define CSR_DFII_RD6_P0			DFII_CSR(0x50)
34  
-#define CSR_DFII_RD7_P0			DFII_CSR(0x54)
35  
-
36  
-#define CSR_DFII_COMMAND_P1		DFII_CSR(0x58)
37  
-#define CSR_DFII_COMMAND_ISSUE_P1	DFII_CSR(0x5C)
38  
-#define CSR_DFII_AH_P1			DFII_CSR(0x60)
39  
-#define CSR_DFII_AL_P1			DFII_CSR(0x64)
40  
-#define CSR_DFII_BA_P1			DFII_CSR(0x68)
41  
-#define CSR_DFII_WD0_P1			DFII_CSR(0x6C)
42  
-#define CSR_DFII_WD1_P1			DFII_CSR(0x70)
43  
-#define CSR_DFII_WD2_P1			DFII_CSR(0x74)
44  
-#define CSR_DFII_WD3_P1			DFII_CSR(0x78)
45  
-#define CSR_DFII_WD4_P1			DFII_CSR(0x7C)
46  
-#define CSR_DFII_WD5_P1			DFII_CSR(0x80)
47  
-#define CSR_DFII_WD6_P1			DFII_CSR(0x84)
48  
-#define CSR_DFII_WD7_P1			DFII_CSR(0x88)
49  
-#define CSR_DFII_RD0_P1			DFII_CSR(0x8C)
50  
-#define CSR_DFII_RD1_P1			DFII_CSR(0x90)
51  
-#define CSR_DFII_RD2_P1			DFII_CSR(0x94)
52  
-#define CSR_DFII_RD3_P1			DFII_CSR(0x98)
53  
-#define CSR_DFII_RD4_P1			DFII_CSR(0x9C)
54  
-#define CSR_DFII_RD5_P1			DFII_CSR(0xA0)
55  
-#define CSR_DFII_RD6_P1			DFII_CSR(0xA4)
56  
-#define CSR_DFII_RD7_P1			DFII_CSR(0xA8)
57  
-
58  
-#define DFII_COMMAND_CS			0x01
59  
-#define DFII_COMMAND_WE			0x02
60  
-#define DFII_COMMAND_CAS		0x04
61  
-#define DFII_COMMAND_RAS		0x08
62  
-#define DFII_COMMAND_WRDATA		0x10
63  
-#define DFII_COMMAND_RDDATA		0x20
64  
-
65  
-#endif /* __HW_DFII_H */
51  software/include/hw/dvisampler.h
... ...
@@ -1,51 +0,0 @@
1  
-#ifndef __HW_DVISAMPLER_H
2  
-#define __HW_DVISAMPLER_H
3  
-
4  
-#include <hw/common.h>
5  
-#include <csrbase.h>
6  
-
7  
-#define DVISAMPLER0_CSR(x)		MMPTR(DVISAMPLER0_BASE+(x))
8  
-
9  
-#define CSR_DVISAMPLER0_PLL_RESET	DVISAMPLER0_CSR(0x00)
10  
-#define CSR_DVISAMPLER0_PLL_LOCKED	DVISAMPLER0_CSR(0x04)
11  
-
12  
-#define CSR_DVISAMPLER0_D0_DELAY_CTL	DVISAMPLER0_CSR(0x08)
13  
-#define CSR_DVISAMPLER0_D0_DELAY_BUSY	DVISAMPLER0_CSR(0x0C)
14  
-#define CSR_DVISAMPLER0_D0_PHASE	DVISAMPLER0_CSR(0x10)
15  
-#define CSR_DVISAMPLER0_D0_PHASE_RESET	DVISAMPLER0_CSR(0x14)
16  
-#define CSR_DVISAMPLER0_D0_CHAR_SYNCED	DVISAMPLER0_CSR(0x18)
17  
-#define CSR_DVISAMPLER0_D0_CTL_POS	DVISAMPLER0_CSR(0x1C)
18  
-
19  
-#define CSR_DVISAMPLER0_D1_DELAY_CTL	DVISAMPLER0_CSR(0x20)
20  
-#define CSR_DVISAMPLER0_D1_DELAY_BUSY	DVISAMPLER0_CSR(0x24)
21  
-#define CSR_DVISAMPLER0_D1_PHASE	DVISAMPLER0_CSR(0x28)
22  
-#define CSR_DVISAMPLER0_D1_PHASE_RESET	DVISAMPLER0_CSR(0x2C)
23  
-#define CSR_DVISAMPLER0_D1_CHAR_SYNCED	DVISAMPLER0_CSR(0x30)
24  
-#define CSR_DVISAMPLER0_D1_CTL_POS	DVISAMPLER0_CSR(0x34)
25  
-
26  
-#define CSR_DVISAMPLER0_D2_DELAY_CTL	DVISAMPLER0_CSR(0x38)
27  
-#define CSR_DVISAMPLER0_D2_DELAY_BUSY	DVISAMPLER0_CSR(0x3C)
28  
-#define CSR_DVISAMPLER0_D2_PHASE	DVISAMPLER0_CSR(0x40)
29  
-#define CSR_DVISAMPLER0_D2_PHASE_RESET	DVISAMPLER0_CSR(0x44)
30  
-#define CSR_DVISAMPLER0_D2_CHAR_SYNCED	DVISAMPLER0_CSR(0x48)
31  
-#define CSR_DVISAMPLER0_D2_CTL_POS	DVISAMPLER0_CSR(0x4C)
32  
-
33  
-#define CSR_DVISAMPLER0_CHAN_SYNCED	DVISAMPLER0_CSR(0x50)
34  
-
35  
-#define CSR_DVISAMPLER0_HRESH		DVISAMPLER0_CSR(0x54)
36  
-#define CSR_DVISAMPLER0_HRESL		DVISAMPLER0_CSR(0x58)
37  
-#define CSR_DVISAMPLER0_VRESH		DVISAMPLER0_CSR(0x5C)
38  
-#define CSR_DVISAMPLER0_VRESL		DVISAMPLER0_CSR(0x60)
39  
-#define CSR_DVISAMPLER0_DECNT2		DVISAMPLER0_CSR(0x64)
40  
-#define CSR_DVISAMPLER0_DECNT1		DVISAMPLER0_CSR(0x68)
41  
-#define CSR_DVISAMPLER0_DECNT0		DVISAMPLER0_CSR(0x6C)
42  
-
43  
-#define DVISAMPLER_DELAY_CAL		0x01
44  
-#define DVISAMPLER_DELAY_RST		0x02
45  
-#define DVISAMPLER_DELAY_INC		0x04
46  
-#define DVISAMPLER_DELAY_DEC		0x08
47  
-
48  
-#define DVISAMPLER_TOO_LATE		0x01
49  
-#define DVISAMPLER_TOO_EARLY		0x02
50  
-
51  
-#endif /* __HW_DVISAMPLER_H */
21  software/include/hw/flags.h
... ...
@@ -0,0 +1,21 @@
  1
+#ifndef __HW_FLAGS_H
  2
+#define __HW_FLAGS_H
  3
+
  4
+#define UART_EV_TX	0x1
  5
+#define UART_EV_RX	0x2
  6
+
  7
+#define DFII_CONTROL_SEL	0x01
  8
+#define DFII_CONTROL_CKE	0x02
  9
+
  10
+#define DFII_COMMAND_CS		0x01
  11
+#define DFII_COMMAND_WE		0x02
  12
+#define DFII_COMMAND_CAS	0x04
  13
+#define DFII_COMMAND_RAS	0x08
  14
+#define DFII_COMMAND_WRDATA	0x10
  15
+#define DFII_COMMAND_RDDATA	0x20
  16
+
  17
+#define MINIMAC_EV_RX0	0x1
  18
+#define MINIMAC_EV_RX1	0x2
  19
+#define MINIMAC_EV_TX	0x4
  20
+
  21
+#endif /* __HW_FLAGS_H */
18  software/include/hw/gpio.h
... ...
@@ -1,18 +0,0 @@
1  
-#ifndef __HW_GPIO_H
2  
-#define __HW_GPIO_H
3  
-
4  
-/* Inputs */
5  
-#define GPIO_BTN1	(0x00000001)
6  
-#define GPIO_BTN2	(0x00000002)
7  
-#define GPIO_BTN3	(0x00000004)
8  
-
9  
-#define GPIO_PCBREV0	(0x00000008)
10  
-#define GPIO_PCBREV1	(0x00000010)
11  
-#define GPIO_PCBREV2	(0x00000020)
12  
-#define GPIO_PCBREV3	(0x00000040)
13  
-
14  
-/* Outputs */
15  
-#define GPIO_LED1	(0x00000001)
16  
-#define GPIO_LED2	(0x00000002)
17  
-
18  
-#endif /* __HW_GPIO_H */
18  software/include/hw/identifier.h
... ...
@@ -1,18 +0,0 @@
1  
-#ifndef __HW_IDENTIFIER_H
2  
-#define __HW_IDENTIFIER_H
3  
-
4  
-#include <hw/common.h>
5  
-#include <csrbase.h>
6  
-
7  
-#define IDENTIFIER_CSR(x)		MMPTR(IDENTIFIER_BASE+(x))
8  
-
9  
-#define CSR_IDENTIFIER_SYSTEMH		IDENTIFIER_CSR(0x00)
10  
-#define CSR_IDENTIFIER_SYSTEML		IDENTIFIER_CSR(0x04)
11  
-#define CSR_IDENTIFIER_VERSIONH		IDENTIFIER_CSR(0x08)
12  
-#define CSR_IDENTIFIER_VERSIONL		IDENTIFIER_CSR(0x0C)
13  
-#define CSR_IDENTIFIER_FREQ3		IDENTIFIER_CSR(0x10)
14  
-#define CSR_IDENTIFIER_FREQ2		IDENTIFIER_CSR(0x14)
15  
-#define CSR_IDENTIFIER_FREQ1		IDENTIFIER_CSR(0x18)
16  
-#define CSR_IDENTIFIER_FREQ0		IDENTIFIER_CSR(0x1C)
17  
-
18  
-#endif /* __HW_IDENTIFIER_H */
4  software/include/hw/mem.h
@@ -17,4 +17,8 @@
17 17
 
18 18
 #define SDRAM_BASE			0x40000000
19 19
 
  20
+#define MINIMAC_RX0_BASE	0xb0000000
  21
+#define MINIMAC_RX1_BASE	0xb0000800
  22
+#define MINIMAC_TX_BASE		0xb0001000
  23
+
20 24
 #endif /* __HW_MEM_H */
32  software/include/hw/minimac.h
... ...
@@ -1,32 +0,0 @@
1  
-#ifndef __HW_MINIMAC_H
2  
-#define __HW_MINIMAC_H
3  
-
4  
-#include <hw/common.h>
5  
-#include <csrbase.h>
6  
-
7  
-#define MINIMAC_CSR(x)		MMPTR(MINIMAC_BASE+(x))
8  
-
9  
-#define CSR_MINIMAC_PHYRST	MINIMAC_CSR(0x00)
10  
-
11  
-#define CSR_MINIMAC_RXCOUNT0H	MINIMAC_CSR(0x04)
12  
-#define CSR_MINIMAC_RXCOUNT0L	MINIMAC_CSR(0x08)
13  
-#define CSR_MINIMAC_RXCOUNT1H	MINIMAC_CSR(0x0C)
14  
-#define CSR_MINIMAC_RXCOUNT1L	MINIMAC_CSR(0x10)
15  
-
16  
-#define CSR_MINIMAC_TXCOUNTH	MINIMAC_CSR(0x14)
17  
-#define CSR_MINIMAC_TXCOUNTL	MINIMAC_CSR(0x18)
18  
-#define CSR_MINIMAC_TXSTART	MINIMAC_CSR(0x1C)
19  
-
20  
-#define CSR_MINIMAC_EV_STAT	MINIMAC_CSR(0x20)
21  
-#define CSR_MINIMAC_EV_PENDING	MINIMAC_CSR(0x24)
22  
-#define CSR_MINIMAC_EV_ENABLE	MINIMAC_CSR(0x28)
23  
-
24  
-#define MINIMAC_EV_RX0		0x1
25  
-#define MINIMAC_EV_RX1		0x2
26  
-#define MINIMAC_EV_TX		0x4
27  
-
28  
-#define MINIMAC_RX0_BASE	0xb0000000
29  
-#define MINIMAC_RX1_BASE	0xb0000800
30  
-#define MINIMAC_TX_BASE		0xb0001000
31  
-
32  
-#endif /* __HW_MINIMAC_H */
27  software/include/hw/timer.h
... ...
@@ -1,27 +0,0 @@
1  
-#ifndef __HW_TIMER_H
2  
-#define __HW_TIMER_H
3  
-
4  
-#include <hw/common.h>
5  
-#include <csrbase.h>
6  
-
7  
-#define TIMER0_CSR(x)		MMPTR(TIMER0_BASE+(x))
8  
-
9  
-#define CSR_TIMER0_EN		TIMER0_CSR(0x00)
10  
-
11  
-#define CSR_TIMER0_COUNT3	TIMER0_CSR(0x04)
12  
-#define CSR_TIMER0_COUNT2	TIMER0_CSR(0x08)
13  
-#define CSR_TIMER0_COUNT1	TIMER0_CSR(0x0C)
14  
-#define CSR_TIMER0_COUNT0	TIMER0_CSR(0x10)
15  
-
16  
-#define CSR_TIMER0_RELOAD3	TIMER0_CSR(0x14)
17  
-#define CSR_TIMER0_RELOAD2	TIMER0_CSR(0x18)
18  
-#define CSR_TIMER0_RELOAD1	TIMER0_CSR(0x1C)
19  
-#define CSR_TIMER0_RELOAD0	TIMER0_CSR(0x20)
20  
-
21  
-#define CSR_TIMER0_EV_STAT	TIMER0_CSR(0x24)
22  
-#define CSR_TIMER0_EV_PENDING	TIMER0_CSR(0x28)
23  
-#define CSR_TIMER0_EV_ENABLE	TIMER0_CSR(0x2C)
24  
-
25  
-#define TIMER0_EV		0x1
26  
-
27  
-#endif /* __HW_TIMER_H */
20  software/include/hw/uart.h
... ...
@@ -1,20 +0,0 @@
1  
-#ifndef __HW_UART_H
2  
-#define __HW_UART_H
3  
-
4  
-#include <hw/common.h>
5  
-#include <csrbase.h>
6  
-
7  
-#define UART_CSR(x)		MMPTR(UART_BASE+(x))
8  
-
9  
-#define CSR_UART_RXTX		UART_CSR(0x00)
10  
-#define CSR_UART_DIVISORH	UART_CSR(0x04)
11  
-#define CSR_UART_DIVISORL	UART_CSR(0x08)
12  
-
13  
-#define CSR_UART_EV_STAT	UART_CSR(0x0c)
14  
-#define CSR_UART_EV_PENDING	UART_CSR(0x10)
15  
-#define CSR_UART_EV_ENABLE	UART_CSR(0x14)
16  
-
17  
-#define UART_EV_TX		0x1
18  
-#define UART_EV_RX		0x2
19  
-
20  
-#endif /* __HW_UART_H */
16  software/libbase/board.c
... ...
@@ -1,5 +1,4 @@
1  
-#include <hw/identifier.h>
2  
-#include <hw/gpio.h>
  1
+#include <hw/csr.h>
3 2
 #include <stdio.h>
4 3
 #include <stdlib.h>
5 4
 #include <string.h>
@@ -27,7 +26,7 @@ static const struct board_desc *get_board_desc_id(unsigned short int id)
27 26
 
28 27
 static const struct board_desc *get_board_desc(void)
29 28
 {
30  
-	return get_board_desc_id((CSR_IDENTIFIER_SYSTEMH << 8) | CSR_IDENTIFIER_SYSTEML);
  29
+	return get_board_desc_id(identifier_sysid_read());
31 30
 }
32 31
 
33 32
 int get_pcb_revision(void)
@@ -54,12 +53,11 @@ void get_soc_version(unsigned int *major, unsigned int *minor, unsigned int *sub
54 53
 {
55 54
 	unsigned int id;
56 55
 
57  
-	id = CSR_IDENTIFIER_VERSIONH;
58  
-	*major = (id & 0xf0) >> 4;
59  
-	*minor = id & 0x0f;
60  
-	id = CSR_IDENTIFIER_VERSIONL;
61  
-	*subminor = (id & 0xf0) >> 4;
62  
-	*rc = id & 0x0f;
  56
+	id = identifier_version_read();
  57
+	*major = (id & 0xf000) >> 12;
  58
+	*minor = (id & 0x0f00) >> 8;
  59
+	*subminor = (id & 0x00f0) >> 4;
  60
+	*rc = id & 0x000f;
63 61
 }
64 62
 
65 63
 void get_soc_version_formatted(char *version)
25  software/libbase/timer.c
... ...
@@ -1,43 +1,30 @@
1  
-#include <hw/timer.h>
2  
-#include <hw/identifier.h>
  1
+#include <hw/csr.h>
3 2
 
4 3
 #include "timer.h"
5 4
 
6 5
 unsigned int get_system_frequency(void)
7 6
 {
8  
-	return (CSR_IDENTIFIER_FREQ3 << 24)
9  
-		|(CSR_IDENTIFIER_FREQ2 << 16)
10  
-		|(CSR_IDENTIFIER_FREQ1 << 8)
11  
-		|CSR_IDENTIFIER_FREQ0;
  7
+	return identifier_frequency_read();
12 8
 }
13 9
 
14 10
 void timer_enable(int en)
15 11
 {
16  
-	CSR_TIMER0_EN = en;
  12
+	timer0_en_write(en);
17 13
 }
18 14
 
19 15
 unsigned int timer_get(void)
20 16
 {
21  
-	return (CSR_TIMER0_COUNT3 << 24)
22  
-		|(CSR_TIMER0_COUNT2 << 16)
23  
-		|(CSR_TIMER0_COUNT1 << 8)
24  
-		|CSR_TIMER0_COUNT0;
  17
+	return timer0_value_read();
25 18
 }
26 19
 
27 20
 void timer_set_counter(unsigned int value)
28 21
 {
29  
-	CSR_TIMER0_COUNT3 = (value & 0xff000000) >> 24;
30  
-	CSR_TIMER0_COUNT2 = (value & 0x00ff0000) >> 16;
31  
-	CSR_TIMER0_COUNT1 = (value & 0x0000ff00) >> 8;
32  
-	CSR_TIMER0_COUNT0 = value & 0x000000ff;
  22
+	timer0_value_write(value);
33 23
 }
34 24
 
35 25
 void timer_set_reload(unsigned int value)
36 26
 {
37  
-	CSR_TIMER0_RELOAD3 = (value & 0xff000000) >> 24;
38  
-	CSR_TIMER0_RELOAD2 = (value & 0x00ff0000) >> 16;
39  
-	CSR_TIMER0_RELOAD1 = (value & 0x0000ff00) >> 8;
40  
-	CSR_TIMER0_RELOAD0 = value & 0x000000ff;
  27
+	timer0_reload_write(value);
41 28
 }
42 29
 
43 30
 void busy_wait(unsigned int ds)
22  software/libbase/uart.c
... ...
@@ -1,7 +1,7 @@
1 1
 #include <uart.h>
2 2
 #include <irq.h>
3  
-#include <hw/uart.h>
4  
-#include <interrupt.h>
  3
+#include <hw/csr.h>
  4
+#include <hw/flags.h>
5 5
 
6 6
 /*
7 7
  * Buffer sizes must be a power of 2 so that modulos can be computed
@@ -28,23 +28,23 @@ void uart_isr(void)
28 28
 {
29 29
 	unsigned int stat;
30 30
 	
31  
-	stat = CSR_UART_EV_PENDING;
  31
+	stat = uart_ev_pending_read();
32 32
 
33 33
 	if(stat & UART_EV_RX) {
34  
-		rx_buf[rx_produce] = CSR_UART_RXTX;
  34
+		rx_buf[rx_produce] = uart_rxtx_read();
35 35
 		rx_produce = (rx_produce + 1) & UART_RINGBUFFER_MASK_RX;
36 36
 	}
37 37
 
38 38
 	if(stat & UART_EV_TX) {
39 39
 		if(tx_level > 0) {
40  
-			CSR_UART_RXTX = tx_buf[tx_consume];
  40
+			uart_rxtx_write(tx_buf[tx_consume]);
41 41
 			tx_consume = (tx_consume + 1) & UART_RINGBUFFER_MASK_TX;
42 42
 			tx_level--;
43 43
 		} else
44 44
 			tx_cts = 1;
45 45
 	}
46 46
 
47  
-	CSR_UART_EV_PENDING = stat;
  47
+	uart_ev_pending_write(stat);
48 48
 }
49 49
 
50 50
 /* Do not use in interrupt handlers! */
@@ -76,7 +76,7 @@ void uart_write(char c)
76 76
 
77 77
 	if(tx_cts) {
78 78
 		tx_cts = 0;
79  
-		CSR_UART_RXTX = c;
  79
+		uart_rxtx_write(c);
80 80
 	} else {
81 81
 		tx_buf[tx_produce] = c;
82 82
 		tx_produce = (tx_produce + 1) & UART_RINGBUFFER_MASK_TX;
@@ -97,12 +97,8 @@ void uart_init(void)
97 97
 	tx_cts = 1;
98 98
 	tx_level = 0;
99 99
 
100  
-	/* ack any events */
101  
-	CSR_UART_EV_PENDING = CSR_UART_EV_PENDING;
102  
-
103  
-	/* enable interrupts */
104  
-	CSR_UART_EV_ENABLE = UART_EV_TX | UART_EV_RX;
105  
-
  100
+	uart_ev_pending_write(uart_ev_pending_read());
  101
+	uart_ev_enable_write(UART_EV_TX | UART_EV_RX);
106 102
 	mask = irq_getmask();
107 103
 	mask |= 1 << UART_INTERRUPT;
108 104
 	irq_setmask(mask);
49  top.py
... ...
@@ -1,5 +1,6 @@
1 1
 from fractions import Fraction
2 2
 from math import ceil
  3
+from operator import itemgetter
3 4
 
4 5
 from migen.fhdl.structure import *
5 6
 from migen.fhdl.module import Module
@@ -8,7 +9,7 @@
8 9
 
9 10
 from milkymist import m1crg, lm32, norflash, uart, s6ddrphy, dfii, asmicon, \
10 11
 	identifier, timer, minimac3, framebuffer, asmiprobe, dvisampler
11  
-from cmacros import get_macros
  12
+from cif import get_macros
12 13
 
13 14
 MHz = 1000000
14 15
 clk_freq = (83 + Fraction(1, 3))*MHz
@@ -46,24 +47,30 @@ def ns(t, margin=True):
46 47
 	write_time=16
47 48
 )
48 49
 
49  
-csr_macros = get_macros("common/csrbase.h")
50  
-def csr_offset(name):
51  
-	base = int(csr_macros[name + "_BASE"], 0)
52  
-	assert((base >= 0xe0000000) and (base <= 0xe0010000))
53  
-	return (base - 0xe0000000)//0x800
54  
-
55  
-interrupt_macros = get_macros("common/interrupt.h")
56  
-def interrupt_n(name):
57  
-	return int(interrupt_macros[name + "_INTERRUPT"], 0)
58  
-
59 50
 version = get_macros("common/version.h")["VERSION"][1:-1]
60 51
 
61  
-def csr_address_map(name, memory):
62  
-	if memory is not None:
63  
-		name += "_" + memory.name_override
64  
-	return csr_offset(name.upper())
65  
-
66 52
 class SoC(Module):
  53
+	csr_base = 0xe0000000
  54
+	csr_map = {
  55
+		"uart":					0,
  56
+		"dfii":					1,
  57
+		"identifier":			2,
  58
+		"timer0":				3,
  59
+		"minimac":				4,
  60
+		"fb":					5,
  61
+		"asmiprobe":			6,
  62
+		"dvisampler0":			7,
  63
+		"dvisampler0_edid_mem":	8,
  64
+		"dvisampler1":			9,
  65
+		"dvisampler1_edid_mem":	10,
  66
+	}
  67
+
  68
+	interrupt_map = {
  69
+		"uart":			0,
  70
+		"timer0":		1,
  71
+		"minimac":		2,
  72
+	}
  73
+
67 74
 	def __init__(self):
68 75
 		#
69 76
 		# ASMI
@@ -122,17 +129,15 @@ def __init__(self):
122 129
 		self.submodules.dvisampler0 = dvisampler.DVISampler("02")
123 130
 		self.submodules.dvisampler1 = dvisampler.DVISampler("02")
124 131
 
125  
-		self.submodules.csrbankarray = csrgen.BankArray(self, csr_address_map)
  132
+		self.submodules.csrbankarray = csrgen.BankArray(self,
  133
+			lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override])
126 134
 		self.submodules.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses())
127 135
 
128 136
 		#
129 137
 		# Interrupts
130 138
 		#
131  
-		self.comb += [
132  
-			self.cpu.interrupt[interrupt_n("UART")].eq(self.uart.ev.irq),
133  
-			self.cpu.interrupt[interrupt_n("TIMER0")].eq(self.timer0.ev.irq),
134  
-			self.cpu.interrupt[interrupt_n("MINIMAC")].eq(self.minimac.ev.irq)
135  
-		]
  139
+		for k, v in sorted(self.interrupt_map.items(), key=itemgetter(1)):
  140
+			self.comb += self.cpu.interrupt[v].eq(getattr(self, k).ev.irq)
136 141
 		
137 142
 		#
138 143
 		# Clocking

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