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  • 4 commits
  • 3 files changed
  • 0 commit comments
  • 1 contributor
View
28 milkymist/framebuffer/__init__.py
@@ -189,6 +189,7 @@ def get_fragment(self):
return Fragment(
[
asfifo.ins["read_en"].eq(1),
+ Cat(self.vga_hsync_n, self.vga_vsync_n, self.vga_r, self.vga_g, self.vga_b).eq(asfifo.outs["data_out"]),
self.endpoints["dac"].ack.eq(~asfifo.outs["full"]),
asfifo.ins["write_en"].eq(self.endpoints["dac"].stb),
@@ -196,8 +197,6 @@ def get_fragment(self):
self.busy.eq(0),
asfifo.ins["rst"].eq(0)
- ], [
- Cat(self.vga_hsync_n, self.vga_vsync_n, self.vga_r, self.vga_g, self.vga_b).eq(asfifo.outs["data_out"])
],
instances=[asfifo])
@@ -205,7 +204,27 @@ def sim_fifo_gen():
while True:
t = sim.Token("dac")
yield t
- print("H/V:" + str(t.value["hsync"]) + str(t.value["vsync"]))
+ print("H/V:" + str(t.value["hsync"]) + str(t.value["vsync"])
+ + " " + str(t.value["r"]) + " " + str(t.value["g"]) + " " + str(t.value["b"]))
+
+class FakeDMA(Actor):
+ def __init__(self, port):
+ self.port = port
+ super().__init__(
+ ("address", Sink, [("a", BV(self.port.hub.aw))]),
+ ("data", Source, [("d", BV(self.port.hub.dw))]))
+
+ def get_fragment(self):
+ pixel = Signal(BV(32))
+ comb = [
+ self.endpoints["address"].ack.eq(1),
+ self.endpoints["data"].stb.eq(1),
+ self.token("data").d.eq(Replicate(pixel, 4))
+ ]
+ sync = [
+ If(self.endpoints["data"].ack, pixel.eq(pixel + 1))
+ ]
+ return Fragment(comb, sync)
class Framebuffer:
def __init__(self, address, asmiport, simulation=False):
@@ -218,7 +237,8 @@ def __init__(self, address, asmiport, simulation=False):
fi = ActorNode(_FrameInitiator(asmi_bits, length_bits, alignment_bits))
adrloop = ActorNode(misc.IntSequence(length_bits, asmi_bits))
adrbuffer = ActorNode(plumbing.Buffer)
- dma = ActorNode(dma_asmi.SequentialReader(asmiport))
+ #dma = ActorNode(dma_asmi.SequentialReader(asmiport))
+ dma = ActorNode(FakeDMA(asmiport))
cast = ActorNode(structuring.Cast(asmiport.hub.dw, packed_pixels))
unpack = ActorNode(structuring.Unpack(pack_factor, _pixel_layout))
vtg = ActorNode(VTG())
View
4 tb/framebuffer/framebuffer.py
@@ -1,6 +1,6 @@
from migen.fhdl.structure import *
from migen.bus import asmibus
-from migen.sim.generic import Simulator, TopLevel
+from migen.sim.generic import Simulator
from migen.sim.icarus import Runner
from milkymist.framebuffer import *
@@ -13,7 +13,7 @@ def main():
dut = Framebuffer(1, port, True)
fragment = hub.get_fragment() + dut.get_fragment()
- sim = Simulator(fragment, Runner(), TopLevel("my.vcd"))
+ sim = Simulator(fragment, Runner())
sim.run(1)
def csr_w(addr, d):
View
9 verilog/generic/asfifo.v
@@ -10,7 +10,7 @@ module asfifo #(
parameter fifo_depth = (1 << address_width)
) (
/* Read port */
- output [data_width-1:0] data_out,
+ output reg [data_width-1:0] data_out,
output reg empty,
input read_en,
input clk_read,
@@ -33,7 +33,12 @@ wire set_status, clear_status;
reg status;
wire preset_full, preset_empty;
-assign data_out = mem[read_index];
+reg [data_width-1:0] data_out0;
+
+always @(posedge clk_read) begin
+ data_out0 <= mem[read_index];
+ data_out <= data_out0;
+end
always @(posedge clk_write) begin
if(write_en & !full)

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