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28  milkymist/framebuffer/__init__.py
@@ -189,6 +189,7 @@ def get_fragment(self):
189 189
 		return Fragment(
190 190
 			[
191 191
 				asfifo.ins["read_en"].eq(1),
  192
+				Cat(self.vga_hsync_n, self.vga_vsync_n, self.vga_r, self.vga_g, self.vga_b).eq(asfifo.outs["data_out"]),
192 193
 				
193 194
 				self.endpoints["dac"].ack.eq(~asfifo.outs["full"]),
194 195
 				asfifo.ins["write_en"].eq(self.endpoints["dac"].stb),
@@ -196,8 +197,6 @@ def get_fragment(self):
196 197
 				
197 198
 				self.busy.eq(0),
198 199
 				asfifo.ins["rst"].eq(0)
199  
-			], [
200  
-				Cat(self.vga_hsync_n, self.vga_vsync_n, self.vga_r, self.vga_g, self.vga_b).eq(asfifo.outs["data_out"])
201 200
 			],
202 201
 			instances=[asfifo])
203 202
 
@@ -205,7 +204,27 @@ def sim_fifo_gen():
205 204
 	while True:
206 205
 		t = sim.Token("dac")
207 206
 		yield t
208  
-		print("H/V:" + str(t.value["hsync"]) + str(t.value["vsync"]))
  207
+		print("H/V:" + str(t.value["hsync"]) + str(t.value["vsync"])
  208
+			+ " " + str(t.value["r"]) + " " + str(t.value["g"]) + " " + str(t.value["b"]))
  209
+
  210
+class FakeDMA(Actor):
  211
+	def __init__(self, port):
  212
+		self.port = port
  213
+		super().__init__(
  214
+				("address", Sink, [("a", BV(self.port.hub.aw))]),
  215
+				("data", Source, [("d", BV(self.port.hub.dw))]))
  216
+	
  217
+	def get_fragment(self):
  218
+		pixel = Signal(BV(32))
  219
+		comb = [
  220
+			self.endpoints["address"].ack.eq(1),
  221
+			self.endpoints["data"].stb.eq(1),
  222
+			self.token("data").d.eq(Replicate(pixel, 4))
  223
+		]
  224
+		sync = [
  225
+			If(self.endpoints["data"].ack, pixel.eq(pixel + 1))
  226
+		]
  227
+		return Fragment(comb, sync)
209 228
 
210 229
 class Framebuffer:
211 230
 	def __init__(self, address, asmiport, simulation=False):
@@ -218,7 +237,8 @@ def __init__(self, address, asmiport, simulation=False):
218 237
 		fi = ActorNode(_FrameInitiator(asmi_bits, length_bits, alignment_bits))
219 238
 		adrloop = ActorNode(misc.IntSequence(length_bits, asmi_bits))
220 239
 		adrbuffer = ActorNode(plumbing.Buffer)
221  
-		dma = ActorNode(dma_asmi.SequentialReader(asmiport))
  240
+		#dma = ActorNode(dma_asmi.SequentialReader(asmiport))
  241
+		dma = ActorNode(FakeDMA(asmiport))
222 242
 		cast = ActorNode(structuring.Cast(asmiport.hub.dw, packed_pixels))
223 243
 		unpack = ActorNode(structuring.Unpack(pack_factor, _pixel_layout))
224 244
 		vtg = ActorNode(VTG())
4  tb/framebuffer/framebuffer.py
... ...
@@ -1,6 +1,6 @@
1 1
 from migen.fhdl.structure import *
2 2
 from migen.bus import asmibus
3  
-from migen.sim.generic import Simulator, TopLevel
  3
+from migen.sim.generic import Simulator
4 4
 from migen.sim.icarus import Runner
5 5
 
6 6
 from milkymist.framebuffer import *
@@ -13,7 +13,7 @@ def main():
13 13
 	dut = Framebuffer(1, port, True)
14 14
 	
15 15
 	fragment = hub.get_fragment() + dut.get_fragment()
16  
-	sim = Simulator(fragment, Runner(), TopLevel("my.vcd"))
  16
+	sim = Simulator(fragment, Runner())
17 17
 	
18 18
 	sim.run(1)
19 19
 	def csr_w(addr, d):
9  verilog/generic/asfifo.v
@@ -10,7 +10,7 @@ module asfifo #(
10 10
 	parameter fifo_depth = (1 << address_width)
11 11
 ) (
12 12
 	/* Read port */
13  
-	output [data_width-1:0] data_out,
  13
+	output reg [data_width-1:0] data_out,
14 14
 	output reg empty,
15 15
 	input read_en,
16 16
 	input clk_read,
@@ -33,7 +33,12 @@ wire set_status, clear_status;
33 33
 reg status;
34 34
 wire preset_full, preset_empty;
35 35
 
36  
-assign data_out = mem[read_index];
  36
+reg [data_width-1:0] data_out0;
  37
+
  38
+always @(posedge clk_read) begin
  39
+	data_out0 <= mem[read_index];
  40
+	data_out <= data_out0;
  41
+end
37 42
 
38 43
 always @(posedge clk_write) begin
39 44
 	if(write_en & !full)

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