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6  constraints.py
... ...
@@ -1,4 +1,4 @@
1  
-def get(ns, reset0, norflash0, uart0):
  1
+def get(ns, clkfx_sys, reset0, norflash0, uart0):
2 2
 	constraints = []
3 3
 	def add(signal, pin, vec=-1, iostandard="LVCMOS33", extra=""):
4 4
 		constraints.append((ns.get_name(signal), vec, pin, iostandard, extra))
@@ -8,6 +8,8 @@ def add_vec(signal, pins, iostandard="LVCMOS33", extra=""):
8 8
 			add(signal, p, i, iostandard, extra)
9 9
 			i += 1
10 10
 	
  11
+	add(clkfx_sys.clkin, "AB11", extra="TNM_NET = \"GRPclk50\"")
  12
+	
11 13
 	add(reset0.trigger_reset, "AA4")
12 14
 	add(reset0.ac97_rst_n, "D6")
13 15
 	add(reset0.videoin_rst_n, "W17")
@@ -39,8 +41,6 @@ def add_vec(signal, pins, iostandard="LVCMOS33", extra=""):
39 41
 		r += ";\n"
40 42
 	
41 43
 	r += """
42  
-NET "sys_clk" LOC = AB11 | IOSTANDARD = LVCMOS33;
43  
-NET "sys_clk" TNM_NET = "GRPclk50";
44 44
 TIMESPEC "TSclk50" = PERIOD "GRPclk50" 20 ns HIGH 50%;
45 45
 	"""
46 46
 	
38  milkymist/clkfx/__init__.py
... ...
@@ -0,0 +1,38 @@
  1
+from fractions import Fraction
  2
+
  3
+from migen.fhdl.structure import *
  4
+
  5
+class Inst:
  6
+	def __init__(self, infreq, outfreq):
  7
+		declare_signal(self, "clkin")
  8
+		declare_signal(self, "clkout")
  9
+		
  10
+		ratio = Fraction(outfreq)/Fraction(infreq)
  11
+		appr = ratio.limit_denominator(32)
  12
+		m = appr.numerator
  13
+		if m < 2 or m > 32:
  14
+			raise OverflowError
  15
+		d = appr.denominator
  16
+		
  17
+		in_period = float(Fraction(1000000000)/Fraction(infreq))
  18
+		
  19
+		self._inst = Instance("DCM_SP",
  20
+			[("CLKFX", self.clkout)],
  21
+			[("CLKIN", self.clkin),
  22
+			("PSEN", BV(1)),
  23
+			("RST", BV(1))],
  24
+			[("CLKDV_DIVIDE", 2.0),
  25
+			("CLKFX_DIVIDE", d),
  26
+			("CLKFX_MULTIPLY", m),
  27
+			("CLKIN_DIVIDE_BY_2", "FALSE"),
  28
+			("CLKIN_PERIOD", in_period),
  29
+			("CLKOUT_PHASE_SHIFT", "NONE"),
  30
+			("CLK_FEEDBACK", "NONE"),
  31
+			("DESKEW_ADJUST", "SYSTEM_SYNCHRONOUS"),
  32
+			("DUTY_CYCLE_CORRECTION", "TRUE"),
  33
+			("PHASE_SHIFT", 0),
  34
+			("STARTUP_WAIT", "TRUE")]
  35
+		)
  36
+
  37
+	def get_fragment(self):
  38
+		return Fragment([self._inst.ins["PSEN"].eq(0), self._inst.ins["RST"].eq(0)], instances=[self._inst])
17  top.py
@@ -2,10 +2,14 @@
2 2
 from migen.fhdl import convtools, verilog, autofragment
3 3
 from migen.bus import wishbone, csr, wishbone2csr
4 4
 
5  
-from milkymist import m1reset, lm32, norflash, uart
  5
+from milkymist import m1reset, clkfx, lm32, norflash, uart
6 6
 import constraints
7 7
 
8 8
 def get():
  9
+	MHz = 1000000
  10
+	clk_freq = 80*MHz
  11
+	
  12
+	clkfx_sys = clkfx.Inst(50*MHz, clk_freq)
9 13
 	reset0 = m1reset.Inst()
10 14
 	
11 15
 	cpu0 = lm32.Inst()
@@ -16,13 +20,16 @@ def get():
16 20
 		[(0, norflash0.bus), (3, wishbone2csr0.wishbone)],
17 21
 		register=True,
18 22
 		offset=1)
19  
-	uart0 = uart.Inst(0, 50*1000*1000, baud=115200)
  23
+	uart0 = uart.Inst(0, clk_freq, baud=115200)
20 24
 	csrcon0 = csr.Interconnect(wishbone2csr0.csr, [uart0.bus])
21 25
 	
22  
-	frag = autofragment.from_local() + Fragment(pads={reset0.trigger_reset})
  26
+	frag = autofragment.from_local()
23 27
 	vns = convtools.Namespace()
24  
-	src_verilog = verilog.Convert(frag, name="soc",
  28
+	src_verilog = verilog.Convert(frag,
  29
+		{clkfx_sys.clkin, reset0.trigger_reset},
  30
+		name="soc",
  31
+		clk_signal=clkfx_sys.clkout,
25 32
 		rst_signal=reset0.sys_rst,
26 33
 		ns=vns)
27  
-	src_ucf = constraints.get(vns, reset0, norflash0, uart0)
  34
+	src_ucf = constraints.get(vns, clkfx_sys, reset0, norflash0, uart0)
28 35
 	return (src_verilog, src_ucf)

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