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  • 3 files changed
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Showing with 53 additions and 8 deletions.
  1. +3 −3 constraints.py
  2. +38 −0 milkymist/clkfx/__init__.py
  3. +12 −5 top.py
View
6 constraints.py
@@ -1,4 +1,4 @@
-def get(ns, reset0, norflash0, uart0):
+def get(ns, clkfx_sys, reset0, norflash0, uart0):
constraints = []
def add(signal, pin, vec=-1, iostandard="LVCMOS33", extra=""):
constraints.append((ns.get_name(signal), vec, pin, iostandard, extra))
@@ -8,6 +8,8 @@ def add_vec(signal, pins, iostandard="LVCMOS33", extra=""):
add(signal, p, i, iostandard, extra)
i += 1
+ add(clkfx_sys.clkin, "AB11", extra="TNM_NET = \"GRPclk50\"")
+
add(reset0.trigger_reset, "AA4")
add(reset0.ac97_rst_n, "D6")
add(reset0.videoin_rst_n, "W17")
@@ -39,8 +41,6 @@ def add_vec(signal, pins, iostandard="LVCMOS33", extra=""):
r += ";\n"
r += """
-NET "sys_clk" LOC = AB11 | IOSTANDARD = LVCMOS33;
-NET "sys_clk" TNM_NET = "GRPclk50";
TIMESPEC "TSclk50" = PERIOD "GRPclk50" 20 ns HIGH 50%;
"""
View
38 milkymist/clkfx/__init__.py
@@ -0,0 +1,38 @@
+from fractions import Fraction
+
+from migen.fhdl.structure import *
+
+class Inst:
+ def __init__(self, infreq, outfreq):
+ declare_signal(self, "clkin")
+ declare_signal(self, "clkout")
+
+ ratio = Fraction(outfreq)/Fraction(infreq)
+ appr = ratio.limit_denominator(32)
+ m = appr.numerator
+ if m < 2 or m > 32:
+ raise OverflowError
+ d = appr.denominator
+
+ in_period = float(Fraction(1000000000)/Fraction(infreq))
+
+ self._inst = Instance("DCM_SP",
+ [("CLKFX", self.clkout)],
+ [("CLKIN", self.clkin),
+ ("PSEN", BV(1)),
+ ("RST", BV(1))],
+ [("CLKDV_DIVIDE", 2.0),
+ ("CLKFX_DIVIDE", d),
+ ("CLKFX_MULTIPLY", m),
+ ("CLKIN_DIVIDE_BY_2", "FALSE"),
+ ("CLKIN_PERIOD", in_period),
+ ("CLKOUT_PHASE_SHIFT", "NONE"),
+ ("CLK_FEEDBACK", "NONE"),
+ ("DESKEW_ADJUST", "SYSTEM_SYNCHRONOUS"),
+ ("DUTY_CYCLE_CORRECTION", "TRUE"),
+ ("PHASE_SHIFT", 0),
+ ("STARTUP_WAIT", "TRUE")]
+ )
+
+ def get_fragment(self):
+ return Fragment([self._inst.ins["PSEN"].eq(0), self._inst.ins["RST"].eq(0)], instances=[self._inst])
View
17 top.py
@@ -2,10 +2,14 @@
from migen.fhdl import convtools, verilog, autofragment
from migen.bus import wishbone, csr, wishbone2csr
-from milkymist import m1reset, lm32, norflash, uart
+from milkymist import m1reset, clkfx, lm32, norflash, uart
import constraints
def get():
+ MHz = 1000000
+ clk_freq = 80*MHz
+
+ clkfx_sys = clkfx.Inst(50*MHz, clk_freq)
reset0 = m1reset.Inst()
cpu0 = lm32.Inst()
@@ -16,13 +20,16 @@ def get():
[(0, norflash0.bus), (3, wishbone2csr0.wishbone)],
register=True,
offset=1)
- uart0 = uart.Inst(0, 50*1000*1000, baud=115200)
+ uart0 = uart.Inst(0, clk_freq, baud=115200)
csrcon0 = csr.Interconnect(wishbone2csr0.csr, [uart0.bus])
- frag = autofragment.from_local() + Fragment(pads={reset0.trigger_reset})
+ frag = autofragment.from_local()
vns = convtools.Namespace()
- src_verilog = verilog.Convert(frag, name="soc",
+ src_verilog = verilog.Convert(frag,
+ {clkfx_sys.clkin, reset0.trigger_reset},
+ name="soc",
+ clk_signal=clkfx_sys.clkout,
rst_signal=reset0.sys_rst,
ns=vns)
- src_ucf = constraints.get(vns, reset0, norflash0, uart0)
+ src_ucf = constraints.get(vns, clkfx_sys, reset0, norflash0, uart0)
return (src_verilog, src_ucf)

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