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32  milkymist/uart/__init__.py
... ...
@@ -1,20 +1,20 @@
1 1
 from migen.fhdl.structure import *
2 2
 from migen.bank.description import *
  3
+from migen.bank.eventmanager import *
3 4
 from migen.bank import csrgen
4 5
 
5 6
 class UART:
6 7
 	def __init__(self, address, clk_freq, baud=115200):
7  
-		self._rxtx = rxtx = Register("rxtx", BV(8))
8  
-		divisor = Register("divisor")
9  
-		self._f_divisor = Field(divisor, "divisor", 8) # TODO: 16
10  
-		stat = Register("stat") # TODO: autogenerated event manager
11  
-		self._f_thre = Field(stat, "thre", access_bus=READ_ONLY, access_dev=WRITE_ONLY)
  8
+		self._rxtx = RegisterRaw("rxtx", 8)
  9
+		self._divisor = RegisterField("divisor", 16, reset=int(clk_freq/baud/16))
12 10
 		
13  
-		self.bank = csrgen.Bank([rxtx, divisor, stat], address=address)
  11
+		self._tx_event = EventSourceLevel()
  12
+		self.events = EventManager(self._tx_event)
  13
+		self.bank = csrgen.Bank([self._rxtx, self._divisor] + self.events.get_registers(),
  14
+			address=address)
  15
+
14 16
 		self.tx = Signal(reset=1)
15 17
 		self.rx = Signal()
16  
-		
17  
-		self.divisor = int(clk_freq/baud/16) # TODO
18 18
 	
19 19
 	def get_fragment(self):
20 20
 		enable16 = Signal()
@@ -25,7 +25,7 @@ def get_fragment(self):
25 25
 		sync = [
26 26
 			enable16_counter.eq(enable16_counter - 1),
27 27
 			If(enable16,
28  
-				enable16_counter.eq(self.divisor - 1)) # TODO
  28
+				enable16_counter.eq(self._divisor.field.r - 1))
29 29
 		]
30 30
 		
31 31
 		tx_reg = Signal(BV(8))
@@ -33,8 +33,8 @@ def get_fragment(self):
33 33
 		tx_count16 = Signal(BV(4))
34 34
 		tx_busy = Signal()
35 35
 		sync += [
36  
-			If(self._rxtx.dev_re,
37  
-				tx_reg.eq(self._rxtx.dev_r),
  36
+			If(self._rxtx.re,
  37
+				tx_reg.eq(self._rxtx.r),
38 38
 				tx_bitcount.eq(0),
39 39
 				tx_count16.eq(1),
40 40
 				tx_busy.eq(1),
@@ -55,10 +55,8 @@ def get_fragment(self):
55 55
 				)
56 56
 			)
57 57
 		]
  58
+		comb.append(self._tx_event.trigger.eq(tx_busy))
58 59
 		
59  
-		comb += [
60  
-			self._f_thre.dev_we.eq(1),
61  
-			self._f_thre.dev_w.eq(~tx_busy)
62  
-		]
63  
-		
64  
-		return self.bank.get_fragment() + Fragment(comb, sync, pads={self.tx, self.rx})
  60
+		return self.bank.get_fragment() \
  61
+			+ self.events.get_fragment() \
  62
+			+ Fragment(comb, sync, pads={self.tx, self.rx})
6  top.py
@@ -39,7 +39,11 @@ def get():
39 39
 	uart0 = uart.UART(0, clk_freq, baud=115200)
40 40
 	csrcon0 = csr.Interconnect(wishbone2csr0.csr, [uart0.bank.interface])
41 41
 	
42  
-	frag = autofragment.from_local()
  42
+	interrupts = Fragment([
  43
+		cpu0.interrupt[0].eq(uart0.events.irq)
  44
+	])
  45
+	
  46
+	frag = autofragment.from_local() + interrupts
43 47
 	src_verilog, vns = verilog.convert(frag,
44 48
 		{clkfx_sys.clkin, reset0.trigger_reset},
45 49
 		name="soc",

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